Author: luporl Date: Thu Nov 5 14:15:50 2020 New Revision: 367383 URL: https://svnweb.freebsd.org/changeset/base/367383
Log: [PowerPC] Make PPC 970 PMC SPRs the standard ones And add a _74XX suffix to 74XX SPRs. This is a preparation for adding support to POWER8/9 PMCs, which have most SPRs equal to 970 ones. Reviewed by: jhibbits Sponsored by: Eldorado Research Institute (eldorado.org.br) Differential Revision: https://reviews.freebsd.org/D26532 Modified: head/sys/dev/hwpmc/hwpmc_mpc7xxx.c head/sys/dev/hwpmc/hwpmc_ppc970.c head/sys/powerpc/include/spr.h head/sys/powerpc/powerpc/cpu.c Modified: head/sys/dev/hwpmc/hwpmc_mpc7xxx.c ============================================================================== --- head/sys/dev/hwpmc/hwpmc_mpc7xxx.c Thu Nov 5 13:45:26 2020 (r367382) +++ head/sys/dev/hwpmc/hwpmc_mpc7xxx.c Thu Nov 5 14:15:50 2020 (r367383) @@ -48,12 +48,15 @@ __FBSDID("$FreeBSD$"); PMC_CAP_WRITE | PMC_CAP_INVERT | \ PMC_CAP_QUALIFIER) -#define PPC_SET_PMC1SEL(r, x) ((r & ~(SPR_MMCR0_PMC1SEL(0x3f))) | SPR_MMCR0_PMC1SEL(x)) -#define PPC_SET_PMC2SEL(r, x) ((r & ~(SPR_MMCR0_PMC2SEL(0x3f))) | SPR_MMCR0_PMC2SEL(x)) +#define PPC_SET_PMC1SEL(r, x) ((r & ~(SPR_MMCR0_74XX_PMC1SEL(0x3f))) | \ + SPR_MMCR0_74XX_PMC1SEL(x)) +#define PPC_SET_PMC2SEL(r, x) ((r & ~(SPR_MMCR0_74XX_PMC2SEL(0x3f))) | \ + SPR_MMCR0_74XX_PMC2SEL(x)) #define PPC_SET_PMC3SEL(r, x) ((r & ~(SPR_MMCR1_PMC3SEL(0x1f))) | SPR_MMCR1_PMC3SEL(x)) #define PPC_SET_PMC4SEL(r, x) ((r & ~(SPR_MMCR1_PMC4SEL(0x1f))) | SPR_MMCR1_PMC4SEL(x)) #define PPC_SET_PMC5SEL(r, x) ((r & ~(SPR_MMCR1_PMC5SEL(0x1f))) | SPR_MMCR1_PMC5SEL(x)) -#define PPC_SET_PMC6SEL(r, x) ((r & ~(SPR_MMCR1_PMC6SEL(0x3f))) | SPR_MMCR1_PMC6SEL(x)) +#define PPC_SET_PMC6SEL(r, x) ((r & ~(SPR_MMCR1_74XX_PMC6SEL(0x3f))) | \ + SPR_MMCR1_74XX_PMC6SEL(x)) /* Change this when we support more than just the 7450. */ #define MPC7XXX_MAX_PMCS 6 @@ -318,22 +321,22 @@ mpc7xxx_pmcn_read(unsigned int pmc) { switch (pmc) { case 0: - return mfspr(SPR_PMC1); + return mfspr(SPR_PMC1_74XX); break; case 1: - return mfspr(SPR_PMC2); + return mfspr(SPR_PMC2_74XX); break; case 2: - return mfspr(SPR_PMC3); + return mfspr(SPR_PMC3_74XX); break; case 3: - return mfspr(SPR_PMC4); + return mfspr(SPR_PMC4_74XX); break; case 4: - return mfspr(SPR_PMC5); + return mfspr(SPR_PMC5_74XX); break; case 5: - return mfspr(SPR_PMC6); + return mfspr(SPR_PMC6_74XX); default: panic("Invalid PMC number: %d\n", pmc); } @@ -344,22 +347,22 @@ mpc7xxx_pmcn_write(unsigned int pmc, uint32_t val) { switch (pmc) { case 0: - mtspr(SPR_PMC1, val); + mtspr(SPR_PMC1_74XX, val); break; case 1: - mtspr(SPR_PMC2, val); + mtspr(SPR_PMC2_74XX, val); break; case 2: - mtspr(SPR_PMC3, val); + mtspr(SPR_PMC3_74XX, val); break; case 3: - mtspr(SPR_PMC4, val); + mtspr(SPR_PMC4_74XX, val); break; case 4: - mtspr(SPR_PMC5, val); + mtspr(SPR_PMC5_74XX, val); break; case 5: - mtspr(SPR_PMC6, val); + mtspr(SPR_PMC6_74XX, val); break; default: panic("Invalid PMC number: %d\n", pmc); @@ -452,34 +455,34 @@ mpc7xxx_start_pmc(int cpu, int ri) /* Enable the PMC. */ switch (ri) { case 0: - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr = PPC_SET_PMC1SEL(pmc_mmcr, config); - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); break; case 1: - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr = PPC_SET_PMC2SEL(pmc_mmcr, config); - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); break; case 2: - pmc_mmcr = mfspr(SPR_MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1_74XX); pmc_mmcr = PPC_SET_PMC3SEL(pmc_mmcr, config); - mtspr(SPR_MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1_74XX, pmc_mmcr); break; case 3: - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr = PPC_SET_PMC4SEL(pmc_mmcr, config); - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); break; case 4: - pmc_mmcr = mfspr(SPR_MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1_74XX); pmc_mmcr = PPC_SET_PMC5SEL(pmc_mmcr, config); - mtspr(SPR_MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1_74XX, pmc_mmcr); break; case 5: - pmc_mmcr = mfspr(SPR_MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1_74XX); pmc_mmcr = PPC_SET_PMC6SEL(pmc_mmcr, config); - mtspr(SPR_MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1_74XX, pmc_mmcr); break; default: break; @@ -490,10 +493,10 @@ mpc7xxx_start_pmc(int cpu, int ri) */ config = ~pm->pm_md.pm_powerpc.pm_powerpc_evsel & POWERPC_PMC_ENABLE; - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr &= ~SPR_MMCR0_FC; pmc_mmcr |= config; - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); return 0; } @@ -513,34 +516,34 @@ mpc7xxx_stop_pmc(int cpu, int ri) */ switch (ri) { case 0: - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr = PPC_SET_PMC1SEL(pmc_mmcr, 0); - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); break; case 1: - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr = PPC_SET_PMC2SEL(pmc_mmcr, 0); - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); break; case 2: - pmc_mmcr = mfspr(SPR_MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1_74XX); pmc_mmcr = PPC_SET_PMC3SEL(pmc_mmcr, 0); - mtspr(SPR_MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1_74XX, pmc_mmcr); break; case 3: - pmc_mmcr = mfspr(SPR_MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0_74XX); pmc_mmcr = PPC_SET_PMC4SEL(pmc_mmcr, 0); - mtspr(SPR_MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0_74XX, pmc_mmcr); break; case 4: - pmc_mmcr = mfspr(SPR_MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1_74XX); pmc_mmcr = PPC_SET_PMC5SEL(pmc_mmcr, 0); - mtspr(SPR_MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1_74XX, pmc_mmcr); break; case 5: - pmc_mmcr = mfspr(SPR_MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1_74XX); pmc_mmcr = PPC_SET_PMC6SEL(pmc_mmcr, 0); - mtspr(SPR_MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1_74XX, pmc_mmcr); break; default: break; @@ -577,9 +580,9 @@ mpc7xxx_pcpu_init(struct pmc_mdep *md, int cpu) } /* Clear the MMCRs, and set FC, to disable all PMCs. */ - mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | + mtspr(SPR_MMCR0_74XX, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE); - mtspr(SPR_MMCR1, 0); + mtspr(SPR_MMCR1_74XX, 0); return 0; } @@ -587,11 +590,11 @@ mpc7xxx_pcpu_init(struct pmc_mdep *md, int cpu) static int mpc7xxx_pcpu_fini(struct pmc_mdep *md, int cpu) { - uint32_t mmcr0 = mfspr(SPR_MMCR0); + uint32_t mmcr0 = mfspr(SPR_MMCR0_74XX); mtmsr(mfmsr() & ~PSL_PMM); mmcr0 |= SPR_MMCR0_FC; - mtspr(SPR_MMCR0, mmcr0); + mtspr(SPR_MMCR0_74XX, mmcr0); free(powerpc_pcpu[cpu]->pc_ppcpmcs, M_PMC); free(powerpc_pcpu[cpu], M_PMC); @@ -678,7 +681,7 @@ mpc7xxx_intr(struct trapframe *tf) pac = powerpc_pcpu[cpu]; - config = mfspr(SPR_MMCR0) & ~SPR_MMCR0_FC; + config = mfspr(SPR_MMCR0_74XX) & ~SPR_MMCR0_FC; /* * look for all PMCs that have interrupted: @@ -717,7 +720,7 @@ mpc7xxx_intr(struct trapframe *tf) /* Re-enable PERF exceptions. */ if (retval) - mtspr(SPR_MMCR0, config | SPR_MMCR0_PMXE); + mtspr(SPR_MMCR0_74XX, config | SPR_MMCR0_PMXE); return (retval); } Modified: head/sys/dev/hwpmc/hwpmc_ppc970.c ============================================================================== --- head/sys/dev/hwpmc/hwpmc_ppc970.c Thu Nov 5 13:45:26 2020 (r367382) +++ head/sys/dev/hwpmc/hwpmc_ppc970.c Thu Nov 5 14:15:50 2020 (r367383) @@ -276,28 +276,28 @@ ppc970_pmcn_read(unsigned int pmc) switch (pmc) { case 0: - val = mfspr(SPR_970PMC1); + val = mfspr(SPR_PMC1); break; case 1: - val = mfspr(SPR_970PMC2); + val = mfspr(SPR_PMC2); break; case 2: - val = mfspr(SPR_970PMC3); + val = mfspr(SPR_PMC3); break; case 3: - val = mfspr(SPR_970PMC4); + val = mfspr(SPR_PMC4); break; case 4: - val = mfspr(SPR_970PMC5); + val = mfspr(SPR_PMC5); break; case 5: - val = mfspr(SPR_970PMC6); + val = mfspr(SPR_PMC6); break; case 6: - val = mfspr(SPR_970PMC7); + val = mfspr(SPR_PMC7); break; case 7: - val = mfspr(SPR_970PMC8); + val = mfspr(SPR_PMC8); break; default: panic("Invalid PMC number: %d\n", pmc); @@ -311,28 +311,28 @@ ppc970_pmcn_write(unsigned int pmc, uint32_t val) { switch (pmc) { case 0: - mtspr(SPR_970PMC1, val); + mtspr(SPR_PMC1, val); break; case 1: - mtspr(SPR_970PMC2, val); + mtspr(SPR_PMC2, val); break; case 2: - mtspr(SPR_970PMC3, val); + mtspr(SPR_PMC3, val); break; case 3: - mtspr(SPR_970PMC4, val); + mtspr(SPR_PMC4, val); break; case 4: - mtspr(SPR_970PMC5, val); + mtspr(SPR_PMC5, val); break; case 5: - mtspr(SPR_970PMC6, val); + mtspr(SPR_PMC6, val); break; case 6: - mtspr(SPR_970PMC7, val); + mtspr(SPR_PMC7, val); break; case 7: - mtspr(SPR_970PMC8, val); + mtspr(SPR_PMC8, val); break; default: panic("Invalid PMC number: %d\n", pmc); @@ -378,9 +378,9 @@ ppc970_set_pmc(int cpu, int ri, int config) switch (ri) { case 0: case 1: - pmc_mmcr = mfspr(SPR_970MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0); pmc_mmcr = PPC970_SET_MMCR0_PMCSEL(pmc_mmcr, config, ri); - mtspr(SPR_970MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0, pmc_mmcr); break; case 2: case 3: @@ -388,9 +388,9 @@ ppc970_set_pmc(int cpu, int ri, int config) case 5: case 6: case 7: - pmc_mmcr = mfspr(SPR_970MMCR1); + pmc_mmcr = mfspr(SPR_MMCR1); pmc_mmcr = PPC970_SET_MMCR1_PMCSEL(pmc_mmcr, config, ri); - mtspr(SPR_970MMCR1, pmc_mmcr); + mtspr(SPR_MMCR1, pmc_mmcr); break; } return 0; @@ -416,10 +416,10 @@ ppc970_start_pmc(int cpu, int ri) */ config = ~pm->pm_md.pm_powerpc.pm_powerpc_evsel & POWERPC_PMC_ENABLE; - pmc_mmcr = mfspr(SPR_970MMCR0); + pmc_mmcr = mfspr(SPR_MMCR0); pmc_mmcr &= ~SPR_MMCR0_FC; pmc_mmcr |= config; - mtspr(SPR_970MMCR0, pmc_mmcr); + mtspr(SPR_MMCR0, pmc_mmcr); return 0; } @@ -505,7 +505,7 @@ ppc970_intr(struct trapframe *tf) * If found, we call a helper to process the interrupt. */ - config = mfspr(SPR_970MMCR0) & ~SPR_MMCR0_FC; + config = mfspr(SPR_MMCR0) & ~SPR_MMCR0_FC; for (i = 0; i < PPC970_MAX_PMCS; i++) { if ((pm = pac->pc_ppcpmcs[i].phw_pmc) == NULL || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { @@ -535,7 +535,7 @@ ppc970_intr(struct trapframe *tf) /* Re-enable PERF exceptions. */ if (retval) - mtspr(SPR_970MMCR0, config | SPR_MMCR0_PMXE); + mtspr(SPR_MMCR0, config | SPR_MMCR0_PMXE); return (retval); } @@ -571,10 +571,10 @@ ppc970_pcpu_init(struct pmc_mdep *md, int cpu) /* Clear the MMCRs, and set FC, to disable all PMCs. */ /* 970 PMC is not counted when set to 0x08 */ - mtspr(SPR_970MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | + mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE | - SPR_970MMCR0_PMC1SEL(0x8) | SPR_970MMCR0_PMC2SEL(0x8)); - mtspr(SPR_970MMCR1, 0x4218420); + SPR_MMCR0_PMC1SEL(0x8) | SPR_MMCR0_PMC2SEL(0x8)); + mtspr(SPR_MMCR1, 0x4218420); return 0; } Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Thu Nov 5 13:45:26 2020 (r367382) +++ head/sys/powerpc/include/spr.h Thu Nov 5 14:15:50 2020 (r367383) @@ -412,6 +412,7 @@ #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ + #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ @@ -441,26 +442,68 @@ #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ -#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ -#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ -#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ -#define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ -#define SPR_970MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ -#define SPR_970MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ -#define SPR_970MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ -#define SPR_970MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ -#define SPR_970MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ -#define SPR_970MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ -#define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ -#define SPR_970PMC1 0x313 /* ... PMC 1 */ -#define SPR_970PMC2 0x314 /* ... PMC 2 */ -#define SPR_970PMC3 0x315 /* ... PMC 3 */ -#define SPR_970PMC4 0x316 /* ... PMC 4 */ -#define SPR_970PMC5 0x317 /* ... PMC 5 */ -#define SPR_970PMC6 0x318 /* ... PMC 6 */ -#define SPR_970PMC7 0x319 /* ... PMC 7 */ -#define SPR_970PMC8 0x31a /* ... PMC 8 */ +#define SPR_MMCRA 0x312 /* ... Monitor Mode Control Register A */ +#define SPR_PMC1 0x313 /* ... PMC 1 */ +#define SPR_PMC2 0x314 /* ... PMC 2 */ +#define SPR_PMC3 0x315 /* ... PMC 3 */ +#define SPR_PMC4 0x316 /* ... PMC 4 */ +#define SPR_PMC5 0x317 /* ... PMC 5 */ +#define SPR_PMC6 0x318 /* ... PMC 6 */ +#define SPR_PMC7 0x319 /* ... PMC 7 */ +#define SPR_PMC8 0x31a /* ... PMC 8 */ +#define SPR_MMCR0 0x31b /* ... Monitor Mode Control Register 0 */ +#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ +#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ +#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ +#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ +#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ +#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ +#define SPR_MMCR0_PMAE 0x04000000 /* PM Alert Enable */ +#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ +#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ +#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ +#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ +#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ +#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ +#define SPR_MMCR0_THRESHOLD(x) ((x) << 16) /* Threshold value */ +#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ +#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ +#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ +#define SPR_MMCR0_PMAO 0x00000080 /* PM Alert Occurred */ +#define SPR_MMCR0_FCPC 0x00001000 /* Freeze Counters in Problem State Cond. */ +#define SPR_MMCR0_FC56 0x00000010 /* Freeze Counters 5-6 */ +#define SPR_MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ +#define SPR_MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ +#define SPR_MMCR0_74XX_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ +#define SPR_MMCR0_74XX_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ + +#define SPR_MMCR1 0x31e /* ... Monitor Mode Control Register 1 */ +#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ +#define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ +#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ +#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ +#define SPR_MMCR1_74XX_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ +#define SPR_MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ +#define SPR_MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ +#define SPR_MMCR1_P8_PMCSEL_ALL 0xffffffff +#define SPR_MMCR1_P8_PMCNSEL_MASK(n) (0xffUL << ((3-(n))*8)) +#define SPR_MMCR1_P8_PMCNSEL(n, v) ((unsigned long)(v) << ((3-(n))*8)) + +#define SPR_MMCR2 0x311 +#define SPR_MMCR2_CNBIT(n, bit) ((bit) << (((5 - (n)) * 9) + 10)) +#define SPR_MMCR2_FCNS(n) SPR_MMCR2_CNBIT(n, 0x100UL) +#define SPR_MMCR2_FCNP0(n) SPR_MMCR2_CNBIT(n, 0x080UL) +#define SPR_MMCR2_FCNP1(n) SPR_MMCR2_CNBIT(n, 0x040UL) +#define SPR_MMCR2_FCNM1(n) SPR_MMCR2_CNBIT(n, 0x020UL) +#define SPR_MMCR2_FCNM0(n) SPR_MMCR2_CNBIT(n, 0x010UL) +#define SPR_MMCR2_FCNWAIT(n) SPR_MMCR2_CNBIT(n, 0x008UL) +#define SPR_MMCR2_FCNH(n) SPR_MMCR2_CNBIT(n, 0x004UL) +/* Freeze Counter N in Hypervisor/Supervisor/Problem states */ +#define SPR_MMCR2_FCNHSP(n) \ + (SPR_MMCR2_FCNS(n) | SPR_MMCR2_FCNP0(n) | \ + SPR_MMCR2_FCNP1(n) | SPR_MMCR2_FCNH(n)) + #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ @@ -502,41 +545,19 @@ #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ -#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ -#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ -#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ -#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ -#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ -#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ -#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ -#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ -#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ -#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ -#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ -#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ -#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ -#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ -#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ -#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ -#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ -#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ -#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ -#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ -#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ -#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ -#define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ -#define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ -#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ -#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ +#define SPR_MMCR2_74XX 0x3b0 /* .6. Monitor Mode Control Register 2 */ +#define SPR_MMCR2_74XX_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ +#define SPR_MMCR2_74XX_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ +#define SPR_PMC5_74XX 0x3b1 /* .6. Performance Counter Register 5 */ +#define SPR_PMC6_74XX 0x3b2 /* .6. Performance Counter Register 6 */ +#define SPR_MMCR0_74XX 0x3b8 /* .6. Monitor Mode Control Register 0 */ +#define SPR_PMC1_74XX 0x3b9 /* .6. Performance Counter Register 1 */ +#define SPR_PMC2_74XX 0x3ba /* .6. Performance Counter Register 2 */ #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ -#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ -#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ -#define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ -#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ -#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ +#define SPR_MMCR1_74XX 0x3bc /* .6. Monitor Mode Control Register 2 */ -#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ -#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ +#define SPR_PMC3_74XX 0x3bd /* .6. Performance Counter Register 3 */ +#define SPR_PMC4_74XX 0x3be /* .6. Performance Counter Register 4 */ #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ Modified: head/sys/powerpc/powerpc/cpu.c ============================================================================== --- head/sys/powerpc/powerpc/cpu.c Thu Nov 5 13:45:26 2020 (r367382) +++ head/sys/powerpc/powerpc/cpu.c Thu Nov 5 14:15:50 2020 (r367383) @@ -377,12 +377,13 @@ cpu_est_clockrate(int cpu_id, uint64_t *cps) case MPC7410: case MPC7447A: case MPC7448: - mtspr(SPR_MMCR0, SPR_MMCR0_FC); - mtspr(SPR_PMC1, 0); - mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); + mtspr(SPR_MMCR0_74XX, SPR_MMCR0_FC); + mtspr(SPR_PMC1_74XX, 0); + mtspr(SPR_MMCR0_74XX, + SPR_MMCR0_74XX_PMC1SEL(PMCN_CYCLES)); DELAY(1000); - *cps = (mfspr(SPR_PMC1) * 1000) + 4999; - mtspr(SPR_MMCR0, SPR_MMCR0_FC); + *cps = (mfspr(SPR_PMC1_74XX) * 1000) + 4999; + mtspr(SPR_MMCR0_74XX, SPR_MMCR0_FC); mtmsr(msr); return (0); @@ -390,18 +391,17 @@ cpu_est_clockrate(int cpu_id, uint64_t *cps) case IBM970FX: case IBM970MP: isync(); - mtspr(SPR_970MMCR0, SPR_MMCR0_FC); + mtspr(SPR_MMCR0, SPR_MMCR0_FC); isync(); - mtspr(SPR_970MMCR1, 0); - mtspr(SPR_970MMCRA, 0); - mtspr(SPR_970PMC1, 0); - mtspr(SPR_970MMCR0, - SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES)); + mtspr(SPR_MMCR1, 0); + mtspr(SPR_MMCRA, 0); + mtspr(SPR_PMC1, 0); + mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMC970N_CYCLES)); isync(); DELAY(1000); powerpc_sync(); - mtspr(SPR_970MMCR0, SPR_MMCR0_FC); - *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; + mtspr(SPR_MMCR0, SPR_MMCR0_FC); + *cps = (mfspr(SPR_PMC1) * 1000) + 4999; mtmsr(msr); return (0); _______________________________________________ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
