Author: gber
Date: Fri Sep 14 09:55:19 2012
New Revision: 240488
URL: http://svn.freebsd.org/changeset/base/240488
Log:
Add support for Armada XP A0.
- Add functions to calculate clocks instead using hardcoded values
- Update reset and timers functions
- Update number of interrupts
- Change name of platform from db88f78100 to db78460
- Correct DRAM size and PCI IRQ routing in dts file.
Obtained from: Semihalf
Added:
head/sys/boot/fdt/dts/db78460.dts (contents, props changed)
Deleted:
head/sys/boot/fdt/dts/db88f78160.dts
Modified:
head/sys/arm/conf/ARMADAXP
head/sys/arm/include/intr.h
head/sys/arm/mv/armadaxp/armadaxp.c
head/sys/arm/mv/common.c
head/sys/arm/mv/mvreg.h
head/sys/arm/mv/mvvar.h
head/sys/arm/mv/mvwin.h
head/sys/arm/mv/timer.c
Modified: head/sys/arm/conf/ARMADAXP
==============================================================================
--- head/sys/arm/conf/ARMADAXP Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/conf/ARMADAXP Fri Sep 14 09:55:19 2012 (r240488)
@@ -99,4 +99,4 @@ device vlan
#FDT
options FDT
options FDT_DTB_STATIC
-makeoptions FDT_DTS_FILE=db88f78160.dts
+makeoptions FDT_DTS_FILE=db78460.dts
Modified: head/sys/arm/include/intr.h
==============================================================================
--- head/sys/arm/include/intr.h Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/include/intr.h Fri Sep 14 09:55:19 2012 (r240488)
@@ -54,6 +54,8 @@
#define NIRQ 128
#elif defined(CPU_ARM11)
#define NIRQ 128
+#elif defined(SOC_MV_ARMADAXP)
+#define NIRQ 148
#else
#define NIRQ 32
#endif
Modified: head/sys/arm/mv/armadaxp/armadaxp.c
==============================================================================
--- head/sys/arm/mv/armadaxp/armadaxp.c Fri Sep 14 09:45:13 2012
(r240487)
+++ head/sys/arm/mv/armadaxp/armadaxp.c Fri Sep 14 09:55:19 2012
(r240488)
@@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <sys/bus.h>
#include <machine/bus.h>
+#include <machine/armreg.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
@@ -43,24 +44,120 @@ __FBSDID("$FreeBSD$");
#include <machine/fdt.h>
+#define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
+ (0x07 & (sar >> 21)))
+#define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
+ (0x0F & (sar >> 24)))
+
+static uint32_t count_l2clk(void);
+
+/* XXX Make gpio driver optional and remove it */
struct resource_spec mv_gpio_res[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
{ -1, 0 }
};
+struct vco_freq_ratio {
+ uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
+ uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */
+ uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */
+ uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */
+};
+
+static struct vco_freq_ratio freq_conf_table[] = {
+/*00*/ { 1, 1, 4, 2 },
+/*01*/ { 1, 2, 2, 2 },
+/*02*/ { 2, 2, 6, 3 },
+/*03*/ { 2, 2, 3, 3 },
+/*04*/ { 1, 2, 3, 3 },
+/*05*/ { 1, 2, 4, 2 },
+/*06*/ { 1, 1, 2, 2 },
+/*07*/ { 2, 3, 6, 6 },
+/*08*/ { 2, 3, 5, 5 },
+/*09*/ { 1, 2, 6, 3 },
+/*10*/ { 2, 4, 10, 5 },
+/*11*/ { 1, 3, 6, 6 },
+/*12*/ { 1, 2, 5, 5 },
+/*13*/ { 1, 3, 6, 3 },
+/*14*/ { 1, 2, 5, 5 },
+/*15*/ { 2, 2, 5, 5 },
+/*16*/ { 1, 1, 3, 3 },
+/*17*/ { 2, 5, 10, 10 },
+/*18*/ { 1, 3, 8, 4 },
+/*19*/ { 1, 1, 2, 1 },
+/*20*/ { 2, 3, 6, 3 },
+/*21*/ { 1, 2, 8, 4 },
+/*22*/ { 2, 5, 10, 5 }
+};
+
+static uint16_t cpu_clock_table[] = {
+ 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
+ 2133, 2200, 2400 };
+
uint32_t
get_tclk(void)
{
+ uint32_t cputype;
- return (TCLK_200MHZ);
+ cputype = cpufunc_id();
+ cputype &= CPU_ID_CPU_MASK;
+
+ if (cputype == CPU_ID_MV88SV584X_V7)
+ return (TCLK_250MHZ);
+ else
+ return (TCLK_200MHZ);
+}
+
+static uint32_t
+count_l2clk(void)
+{
+ uint64_t sar_reg;
+ uint32_t freq_vco, freq_l2clk;
+ uint8_t sar_cpu_freq, sar_fab_freq, array_size;
+
+ /* Get value of the SAR register and process it */
+ sar_reg = get_sar_value();
+ sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
+ sar_fab_freq = FAB_FREQ_FIELD(sar_reg);
+
+ /* Check if CPU frequency field has correct value */
+ array_size = sizeof(cpu_clock_table) / sizeof(cpu_clock_table[0]);
+ if (sar_cpu_freq >= array_size)
+ panic("Reserved value in cpu frequency configuration field: "
+ "%d", sar_cpu_freq);
+
+ /* Check if fabric frequency field has correct value */
+ array_size = sizeof(freq_conf_table) / sizeof(freq_conf_table[0]);
+ if (sar_fab_freq >= array_size)
+ panic("Reserved value in fabric frequency configuration field: "
+ "%d", sar_fab_freq);
+
+ /* Get CPU clock frequency */
+ freq_vco = cpu_clock_table[sar_cpu_freq] *
+ freq_conf_table[sar_fab_freq].vco_cpu;
+
+ /* Get L2CLK clock frequency */
+ freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c;
+
+ /* Round L2CLK value to integer MHz */
+ if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 /
+ freq_conf_table[sar_fab_freq].vco_l2c) >= 5)
+ freq_l2clk++;
+
+ return (freq_l2clk * 1000000);
}
uint32_t
get_l2clk(void)
{
+ static uint32_t l2clk_freq = 0;
+
+ /* If get_l2clk is called first time get L2CLK value from register */
+ if (l2clk_freq == 0)
+ l2clk_freq = count_l2clk();
- return (TCLK_667MHZ);
+ return (l2clk_freq);
}
int
Modified: head/sys/arm/mv/common.c
==============================================================================
--- head/sys/arm/mv/common.c Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/mv/common.c Fri Sep 14 09:55:19 2012 (r240488)
@@ -249,12 +249,47 @@ write_cpu_ctrl(uint32_t reg, uint32_t va
bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
}
+#if defined(SOC_MV_ARMADAXP)
+uint32_t
+read_cpu_mp_clocks(uint32_t reg)
+{
+
+ return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
+}
+
+void
+write_cpu_mp_clocks(uint32_t reg, uint32_t val)
+{
+
+ bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);
+}
+
+uint32_t
+read_cpu_misc(uint32_t reg)
+{
+
+ return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));
+}
+
+void
+write_cpu_misc(uint32_t reg, uint32_t val)
+{
+
+ bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
+}
+#endif
+
void
cpu_reset(void)
{
+#if defined(SOC_MV_ARMADAXP)
+ write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
+ write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
+#else
write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
+#endif
while (1);
}
@@ -2062,19 +2097,26 @@ fdt_fixup_busfreq(phandle_t root)
phandle_t sb;
pcell_t freq;
+ freq = cpu_to_fdt32(get_tclk());
+
/*
- * This fixup sets the simple-bus bus-frequency property.
+ * Fix bus speed in cpu node
*/
+ if ((sb = OF_finddevice("cpu")) != 0)
+ if (fdt_is_compatible_strict(sb, "ARM,88VS584"))
+ OF_setprop(sb, "bus-frequency", (void *)&freq,
+ sizeof(freq));
- if ((sb = fdt_find_compatible(root, "simple-bus", 1)) == 0)
- return;
-
- freq = cpu_to_fdt32(get_tclk());
- OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
+ /*
+ * This fixup sets the simple-bus bus-frequency property.
+ */
+ if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)
+ OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
}
struct fdt_fixup_entry fdt_fixup_table[] = {
{ "mrvl,DB-88F6281", &fdt_fixup_busfreq },
+ { "mrvl,DB-78460", &fdt_fixup_busfreq },
{ NULL, NULL }
};
@@ -2098,3 +2140,24 @@ fdt_pic_decode_t fdt_pic_table[] = {
&fdt_pic_decode_ic,
NULL
};
+
+uint64_t
+get_sar_value(void)
+{
+ uint32_t sar_low, sar_high;
+
+#if defined(SOC_MV_ARMADAXP)
+ sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
+ SAMPLE_AT_RESET_HI);
+ sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
+ SAMPLE_AT_RESET_LO);
+#else
+ /*
+ * TODO: Add getting proper values for other SoC configurations
+ */
+ sar_high = 0;
+ sar_low = 0;
+#endif
+
+ return (((uint64_t)sar_high << 32) | sar_low);
+}
Modified: head/sys/arm/mv/mvreg.h
==============================================================================
--- head/sys/arm/mv/mvreg.h Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/mv/mvreg.h Fri Sep 14 09:55:19 2012 (r240488)
@@ -123,11 +123,21 @@
/*
* System reset
*/
+#if defined(SOC_MV_ARMADAXP)
+#define RSTOUTn_MASK 0x60
+#define SYSTEM_SOFT_RESET 0x64
+#define WD_RSTOUTn_MASK 0x4
+#define WD_GLOBAL_MASK 0x00000100
+#define WD_CPU0_MASK 0x00000001
+#define SOFT_RST_OUT_EN 0x00000001
+#define SYS_SOFT_RST 0x00000001
+#else
#define RSTOUTn_MASK 0x8
#define WD_RST_OUT_EN 0x00000002
#define SOFT_RST_OUT_EN 0x00000004
#define SYSTEM_SOFT_RESET 0xc
#define SYS_SOFT_RST 0x00000001
+#endif
/*
* Power Control
@@ -334,6 +344,9 @@
#define SAMPLE_AT_RESET_HI 0x18
#elif defined(SOC_MV_FREY)
#define SAMPLE_AT_RESET 0x100
+#elif defined(SOC_MV_ARMADAXP)
+#define SAMPLE_AT_RESET_LO 0x30
+#define SAMPLE_AT_RESET_HI 0x34
#endif
/*
Modified: head/sys/arm/mv/mvvar.h
==============================================================================
--- head/sys/arm/mv/mvvar.h Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/mv/mvvar.h Fri Sep 14 09:55:19 2012 (r240488)
@@ -89,6 +89,7 @@ void soc_id(uint32_t *dev, uint32_t *rev
void soc_dump_decode_win(void);
uint32_t soc_power_ctrl_get(uint32_t mask);
void soc_power_ctrl_set(uint32_t mask);
+uint64_t get_sar_value(void);
int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
vm_paddr_t remap);
@@ -108,6 +109,13 @@ uint32_t get_l2clk(void);
uint32_t read_cpu_ctrl(uint32_t);
void write_cpu_ctrl(uint32_t, uint32_t);
+#if defined(SOC_MV_ARMADAXP)
+uint32_t read_cpu_mp_clocks(uint32_t reg);
+void write_cpu_mp_clocks(uint32_t reg, uint32_t val);
+uint32_t read_cpu_misc(uint32_t reg);
+void write_cpu_misc(uint32_t reg, uint32_t val);
+#endif
+
int mv_pcib_bar_win_set(device_t dev, uint32_t base, uint32_t size,
uint32_t remap, int winno, int busno);
int mv_pcib_cpu_win_remap(device_t dev, uint32_t remap, uint32_t size);
Modified: head/sys/arm/mv/mvwin.h
==============================================================================
--- head/sys/arm/mv/mvwin.h Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/mv/mvwin.h Fri Sep 14 09:55:19 2012 (r240488)
@@ -128,8 +128,10 @@
#define MV_MPP_BASE (MV_BASE + 0x10000)
#if defined(SOC_MV_ARMADAXP)
+#define MV_MISC_BASE (MV_BASE + 0x18200)
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
+#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700)
#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800)
#elif !defined(SOC_MV_FREY)
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
Modified: head/sys/arm/mv/timer.c
==============================================================================
--- head/sys/arm/mv/timer.c Fri Sep 14 09:45:13 2012 (r240487)
+++ head/sys/arm/mv/timer.c Fri Sep 14 09:55:19 2012 (r240488)
@@ -311,15 +311,19 @@ mv_watchdog_enable(void)
irq_cause &= IRQ_TIMER_WD_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
-#if !defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP)
+ val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
+ val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
+ write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
+#else
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask |= IRQ_TIMER_WD_MASK;
write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
-#endif
val = read_cpu_ctrl(RSTOUTn_MASK);
val |= WD_RST_OUT_EN;
write_cpu_ctrl(RSTOUTn_MASK, val);
+#endif
val = mv_get_timer_control();
val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
@@ -338,11 +342,15 @@ mv_watchdog_disable(void)
val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
mv_set_timer_control(val);
+#if defined(SOC_MV_ARMADAXP)
+ val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
+ val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
+ write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
+#else
val = read_cpu_ctrl(RSTOUTn_MASK);
val &= ~WD_RST_OUT_EN;
write_cpu_ctrl(RSTOUTn_MASK, val);
-#if !defined(SOC_MV_ARMADAXP)
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask &= ~(IRQ_TIMER_WD_MASK);
write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
Added: head/sys/boot/fdt/dts/db78460.dts
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/db78460.dts Fri Sep 14 09:55:19 2012
(r240488)
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * Copyright (c) 2010-2011 Semihalf
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-78460 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-78460";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "ARM,88VS584";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <200000000>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x80000000>; // 2G at 0x0
+ };
+
+ soc78460@d0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xd0000000 0x00100000>;
+ bus-frequency = <0>;
+
+
+ MPIC: mpic@20a00 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20a00 0x500 0x21000 0x800>;
+ compatible = "mrvl,mpic";
+ };
+
+ rtc@10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ timer@21840 {
+ compatible = "mrvl,timer";
+ reg = <0x21840 0x30>;
+ interrupts = <5>;
+ interrupt-parent = <&MPIC>;
+ mrvl,has-wdt;
+ };
+
+ twsi@11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <31>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ twsi@11100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11100 0x20>;
+ interrupts = <32>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial0: serial@12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ interrupts = <41>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial1: serial@12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ interrupts = <42>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial2: serial@12200 {
+ compatible = "ns16550";
+ reg = <0x12200 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ interrupts = <43>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ serial3: serial@12300 {
+ compatible = "ns16550";
+ reg = <0x12300 0x20>;
+ reg-shift = <2>;
+ current-speed = <115200>;
+ clock-frequency = <0>;
+ interrupts = <44>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ MPP: mpp@10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x18000 0x34>;
+ pin-count = <68>;
+ pin-map = <
+ 0 1 /* MPP[0]: GE1_TXCLK */
+ 1 1 /* MPP[1]: GE1_TXCTL */
+ 2 1 /* MPP[2]: GE1_RXCTL */
+ 3 1 /* MPP[3]: GE1_RXCLK */
+ 4 1 /* MPP[4]: GE1_TXD[0] */
+ 5 1 /* MPP[5]: GE1_TXD[1] */
+ 6 1 /* MPP[6]: GE1_TXD[2] */
+ 7 1 /* MPP[7]: GE1_TXD[3] */
+ 8 1 /* MPP[8]: GE1_RXD[0] */
+ 9 1 /* MPP[9]: GE1_RXD[1] */
+ 10 1 /* MPP[10]: GE1_RXD[2] */
+ 11 1 /* MPP[11]: GE1_RXD[3] */
+ 12 2 /* MPP[13]: SYSRST_OUTn */
+ 13 2 /* MPP[13]: SYSRST_OUTn */
+ 14 2 /* MPP[14]: SATA1_ACTn */
+ 15 2 /* MPP[15]: SATA0_ACTn */
+ 16 2 /* MPP[16]: UA2_TXD */
+ 17 2 /* MPP[17]: UA2_RXD */
+ 18 2 /* MPP[18]: <UNKNOWN> */
+ 19 2 /* MPP[19]: <UNKNOWN> */
+ 20 2 /* MPP[20]: <UNKNOWN> */
+ 21 2 /* MPP[21]: <UNKNOWN> */
+ 22 2 /* MPP[22]: UA3_TXD */
+ 23 2
+ 24 0
+ 25 0
+ 26 0
+ 27 0
+ 28 4
+ 29 0
+ 30 1
+ 31 1
+ 32 1
+ 33 1
+ 34 1
+ 35 1
+ 36 1
+ 37 1
+ 38 1
+ 39 1
+ 40 0
+ 41 3
+ 42 1
+ 43 1
+ 44 2
+ 45 2
+ 46 4
+ 47 3
+ 48 0
+ 49 1
+ 50 1
+ 51 1
+ 52 1
+ 53 1
+ 54 1
+ 55 1
+ 56 1
+ 57 0
+ 58 1
+ 59 1
+ 60 1
+ 61 1
+ 62 1
+ 63 1
+ 64 1
+ 65 1
+ 66 1
+ 67 2 >;
+ };
+
+ usb@50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <124 45>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ usb@51000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x51000 0x1000>;
+ interrupts = <124 46>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ usb@52000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x52000 0x1000>;
+ interrupts = <124 47>;
+ interrupt-parent = <&MPIC>;
+ };
+
+ enet0: ethernet@72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 04 01 07 84 60 ];
+ interrupts = <67 68 122 >;
+ interrupt-parent = <&MPIC>;
+ phy-handle = <&phy0>;
+ has-neta;
+
+ mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <0x19>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <0x1b>;
+ };
+ };
+ };
+ };
+
+ pci0: pcie@d0040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xd0040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xa0000000 0x0 0x08000000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <120>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0800 0x0 0x0 0x1 &MPIC 0x3A
+ 0x0800 0x0 0x0 0x2 &MPIC 0x3A
+ 0x0800 0x0 0x0 0x3 &MPIC 0x3A
+ 0x0800 0x0 0x0 0x4 &MPIC 0x3A
+ >;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ stddbg = "serial0";
+ };
+};
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