Author: tychon
Date: Fri Jun 6 16:18:37 2014
New Revision: 267169
URL: http://svnweb.freebsd.org/changeset/base/267169
Log:
Some devices (e.g. Intel AHCI and NICs) support quad-word access to
register pairs where two 32-bit registers make up a larger logical
size. Support those access by splitting the quad-word into two
double-words.
Reviewed by: grehan
Modified:
head/usr.sbin/bhyve/pci_emul.c
Modified: head/usr.sbin/bhyve/pci_emul.c
==============================================================================
--- head/usr.sbin/bhyve/pci_emul.c Fri Jun 6 15:17:19 2014
(r267168)
+++ head/usr.sbin/bhyve/pci_emul.c Fri Jun 6 16:18:37 2014
(r267169)
@@ -375,10 +375,27 @@ pci_emul_mem_handler(struct vmctx *ctx,
offset = addr - pdi->pi_bar[bidx].addr;
- if (dir == MEM_F_WRITE)
- (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val);
- else
- *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size);
+ if (dir == MEM_F_WRITE) {
+ if (pdi->pi_bar[bidx].type == PCIBAR_MEM32 && size == 8) {
+ (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
+ 4, *val & 0xffffffff);
+ (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
+ 4, *val >> 32);
+ } else {
+ (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
+ size, *val);
+ }
+ } else {
+ if (pdi->pi_bar[bidx].type == PCIBAR_MEM32 && size == 8) {
+ *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
+ offset, 4);
+ *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
+ offset + 4, 4) << 32;
+ } else {
+ *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
+ offset, size);
+ }
+ }
return (0);
}
_______________________________________________
svn-src-head@freebsd.org mailing list
http://lists.freebsd.org/mailman/listinfo/svn-src-head
To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
