Author: sbruno
Date: Thu Jan 8 16:50:35 2015
New Revision: 276834
URL: https://svnweb.freebsd.org/changeset/base/276834
Log:
Update Features2 to display SDBG capability of processor. This is
showing up on Haswell-class CPUs
From the Intel SDM, "Table 3-20. Feature Information Returned in the
ECX Register"
11 | SDBG | A value of 1 indicates the processor supports
IA32_DEBUG_INTERFACE MSR for silicon debug.
Submitted by: jiash...@gmail.com
Reviewed by: jhb neel
MFC after: 2 weeks
Modified:
head/sys/x86/include/specialreg.h
head/sys/x86/x86/identcpu.c
Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h Thu Jan 8 16:35:09 2015
(r276833)
+++ head/sys/x86/include/specialreg.h Thu Jan 8 16:50:35 2015
(r276834)
@@ -154,6 +154,7 @@
#define CPUID2_TM2 0x00000100
#define CPUID2_SSSE3 0x00000200
#define CPUID2_CNXTID 0x00000400
+#define CPUID2_SDBG 0x00000800
#define CPUID2_FMA 0x00001000
#define CPUID2_CX16 0x00002000
#define CPUID2_XTPR 0x00004000
Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c Thu Jan 8 16:35:09 2015 (r276833)
+++ head/sys/x86/x86/identcpu.c Thu Jan 8 16:50:35 2015 (r276834)
@@ -781,7 +781,7 @@ printcpuinfo(void)
"\011TM2" /* Thermal Monitor 2 */
"\012SSSE3" /* SSSE3 */
"\013CNXT-ID" /* L1 context ID available */
- "\014<b11>"
+ "\014SDBG" /* IA32 silicon debug */
"\015FMA" /* Fused Multiply Add */
"\016CX16" /* CMPXCHG16B Instruction */
"\017xTPR" /* Send Task Priority Messages*/
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