Author: jmcneill
Date: Fri Apr 8 10:54:59 2016
New Revision: 297703
URL: https://svnweb.freebsd.org/changeset/base/297703
Log:
Add function for mapping SRAM-D area to USB0 (OTG) controller. Use a lower
pass number to ensure that this driver is loaded before EMAC or OTG,
regardless of the order of nodes in the DT.
Modified:
head/sys/arm/allwinner/a10_sramc.c
head/sys/arm/allwinner/a10_sramc.h
Modified: head/sys/arm/allwinner/a10_sramc.c
==============================================================================
--- head/sys/arm/allwinner/a10_sramc.c Fri Apr 8 10:23:48 2016
(r297702)
+++ head/sys/arm/allwinner/a10_sramc.c Fri Apr 8 10:54:59 2016
(r297703)
@@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
#include "a10_sramc.h"
#define SRAM_CTL1_CFG 0x04
+#define CTL1_CFG_SRAMD_MAP_USB0 (1 << 0)
struct a10_sramc_softc {
struct resource *res;
@@ -113,7 +114,8 @@ static driver_t a10_sramc_driver = {
static devclass_t a10_sramc_devclass;
-DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, a10_sramc_devclass, 0,
0);
+EARLY_DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, a10_sramc_devclass,
+ 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_EARLY);
int
a10_map_to_emac(void)
@@ -131,3 +133,20 @@ a10_map_to_emac(void)
return (0);
}
+
+int
+a10_map_to_otg(void)
+{
+ struct a10_sramc_softc *sc = a10_sramc_sc;
+ uint32_t reg_value;
+
+ if (sc == NULL)
+ return (ENXIO);
+
+ /* Map SRAM to OTG */
+ reg_value = sramc_read_4(sc, SRAM_CTL1_CFG);
+ reg_value |= CTL1_CFG_SRAMD_MAP_USB0;
+ sramc_write_4(sc, SRAM_CTL1_CFG, reg_value);
+
+ return (0);
+}
Modified: head/sys/arm/allwinner/a10_sramc.h
==============================================================================
--- head/sys/arm/allwinner/a10_sramc.h Fri Apr 8 10:23:48 2016
(r297702)
+++ head/sys/arm/allwinner/a10_sramc.h Fri Apr 8 10:54:59 2016
(r297703)
@@ -30,5 +30,6 @@
#define _A10_SRAMC_H_
int a10_map_to_emac(void);
+int a10_map_to_otg(void);
#endif
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