Author: adrian
Date: Thu May 12 15:18:36 2016
New Revision: 299534
URL: https://svnweb.freebsd.org/changeset/base/299534
Log:
[siba] add extra methods for chipcommon access and PLL configuration.
This is needed by the PHY-N bwn(4) support.
Obtained from: Linux b43 (definitions)
Modified:
head/sys/dev/siba/siba_core.c
head/sys/dev/siba/sibareg.h
head/sys/dev/siba/sibavar.h
Modified: head/sys/dev/siba/siba_core.c
==============================================================================
--- head/sys/dev/siba/siba_core.c Thu May 12 14:41:53 2016
(r299533)
+++ head/sys/dev/siba/siba_core.c Thu May 12 15:18:36 2016
(r299534)
@@ -2720,3 +2720,124 @@ siba_sprom_get_core_power_info(device_t
return (0);
}
+void
+siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid)
+{
+ struct siba_dev_softc *sd = device_get_ivars(dev);
+ struct siba_softc *siba = sd->sd_bus;
+ struct siba_cc *scc;
+
+ scc = &siba->siba_cc;
+
+ if (scc->scc_dev == NULL) {
+ device_printf(dev, "%s: called; no pmu\n", __func__);
+ return;
+ }
+
+ switch (siba_get_chipid(dev)) {
+ case 0x4322:
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854);
+ if (spur_avoid == 1)
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828);
+ else
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828);
+ break;
+ case 43222:
+ if (spur_avoid == 1) {
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815);
+ } else {
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0);
+ siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855);
+ }
+ break;
+ default:
+ device_printf(dev,
+ "%s: unknown spur avoidance settings for chip 0x%04x\n",
+ __func__,
+ siba_get_chipid(dev));
+ return;
+ }
+
+ /* Both chips above use the same update */
+ SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD);
+}
+
+void
+siba_cc_set32(device_t dev, uint32_t reg, uint32_t val)
+{
+ struct siba_dev_softc *sd = device_get_ivars(dev);
+ struct siba_softc *siba = sd->sd_bus;
+ struct siba_cc *scc;
+
+ scc = &siba->siba_cc;
+
+ if (scc->scc_dev == NULL) {
+ device_printf(dev, "%s: called; no pmu\n", __func__);
+ return;
+ }
+
+ SIBA_CC_SET32(scc, reg, val);
+}
+
+void
+siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask)
+{
+ struct siba_dev_softc *sd = device_get_ivars(dev);
+ struct siba_softc *siba = sd->sd_bus;
+ struct siba_cc *scc;
+
+ scc = &siba->siba_cc;
+
+ if (scc->scc_dev == NULL) {
+ device_printf(dev, "%s: called; no pmu\n", __func__);
+ return;
+ }
+
+ SIBA_CC_MASK32(scc, reg, mask);
+}
+
+uint32_t
+siba_cc_read32(device_t dev, uint32_t reg)
+{
+ struct siba_dev_softc *sd = device_get_ivars(dev);
+ struct siba_softc *siba = sd->sd_bus;
+ struct siba_cc *scc;
+
+ scc = &siba->siba_cc;
+
+ if (scc->scc_dev == NULL) {
+ device_printf(dev, "%s: called; no pmu\n", __func__);
+ return 0xffffffff;
+ }
+
+ return SIBA_CC_READ32(scc, reg);
+}
+
+void
+siba_cc_write32(device_t dev, uint32_t reg, uint32_t val)
+{
+ struct siba_dev_softc *sd = device_get_ivars(dev);
+ struct siba_softc *siba = sd->sd_bus;
+ struct siba_cc *scc;
+
+ scc = &siba->siba_cc;
+
+ if (scc->scc_dev == NULL) {
+ device_printf(dev, "%s: called; no pmu\n", __func__);
+ return;
+ }
+
+ SIBA_CC_WRITE32(scc, reg, val);
+}
+
Modified: head/sys/dev/siba/sibareg.h
==============================================================================
--- head/sys/dev/siba/sibareg.h Thu May 12 14:41:53 2016 (r299533)
+++ head/sys/dev/siba/sibareg.h Thu May 12 15:18:36 2016 (r299534)
@@ -81,6 +81,7 @@
#define SIBA_CC_UART0 0x0300 /* offset of
UART0 */
#define SIBA_CC_UART1 0x0400 /* offset of
UART1 */
#define SIBA_CC_PMUCTL 0x0600 /* PMU control
*/
+#define SIBA_CC_PMUCTL_PLL_UPD 0x00000400
#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */
#define SIBA_CC_PMUCTL_NOILP 0x00000200
#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq
*/
@@ -92,6 +93,8 @@
#define SIBA_CC_PMU_TABSEL 0x0620
#define SIBA_CC_PMU_DEPMSK 0x0624
#define SIBA_CC_PMU_UPDNTM 0x0628
+#define SIBA_CC_CHIPCTL_ADDR 0x0650
+#define SIBA_CC_CHIPCTL_DATA 0x0654
#define SIBA_CC_REGCTL_ADDR 0x0658
#define SIBA_CC_REGCTL_DATA 0x065c
#define SIBA_CC_PLLCTL_ADDR 0x0660
@@ -109,11 +112,13 @@
#define SIBA_CC_PMU1_PLL0 0
#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000
#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000
+#define SIBA_CC_PMU1_PLL1 1
#define SIBA_CC_PMU1_PLL2 2
#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000
#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000
#define SIBA_CC_PMU1_PLL3 3
#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff
+#define SIBA_CC_PMU1_PLL4 4
#define SIBA_CC_PMU1_PLL5 5
#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00
Modified: head/sys/dev/siba/sibavar.h
==============================================================================
--- head/sys/dev/siba/sibavar.h Thu May 12 14:41:53 2016 (r299533)
+++ head/sys/dev/siba/sibavar.h Thu May 12 15:18:36 2016 (r299534)
@@ -611,5 +611,10 @@ uint32_t siba_gpio_get(device_t);
void siba_fix_imcfglobug(device_t);
int siba_sprom_get_core_power_info(device_t, int,
struct siba_sprom_core_pwr_info *);
+void siba_pmu_spuravoid_pllupdate(device_t, int);
+void siba_cc_set32(device_t dev, uint32_t, uint32_t);
+void siba_cc_mask32(device_t dev, uint32_t, uint32_t);
+uint32_t siba_cc_read32(device_t dev, uint32_t);
+void siba_cc_write32(device_t dev, uint32_t, uint32_t);
#endif /* _SIBA_SIBAVAR_H_ */
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