Author: jhibbits Date: Tue May 1 04:31:17 2018 New Revision: 333135 URL: https://svnweb.freebsd.org/changeset/base/333135
Log: Remove dead errata fixup code This code caused more problems than it should have fixed (boot failures) on the machines I tested, so has been commented out for a while now. Remove it, and assume the errata fixups were done by the bootloader where they belong. Modified: head/sys/powerpc/booke/locore.S head/sys/powerpc/mpc85xx/mpc85xx.c head/sys/powerpc/mpc85xx/mpc85xx.h head/sys/powerpc/mpc85xx/platform_mpc85xx.c Modified: head/sys/powerpc/booke/locore.S ============================================================================== --- head/sys/powerpc/booke/locore.S Tue May 1 04:06:59 2018 (r333134) +++ head/sys/powerpc/booke/locore.S Tue May 1 04:31:17 2018 (r333135) @@ -906,68 +906,6 @@ ENTRY(bpred_enable) isync blr -ENTRY(dataloss_erratum_access) - /* Lock two cache lines into I-Cache */ - sync - mfspr %r11, SPR_L1CSR1 - rlwinm %r11, %r11, 0, ~L1CSR1_ICUL - sync - isync - mtspr SPR_L1CSR1, %r11 - isync - - lis %r8, 2f@h - ori %r8, %r8, 2f@l - icbtls 0, 0, %r8 - addi %r9, %r8, 64 - - sync - mfspr %r11, SPR_L1CSR1 -3: andi. %r11, %r11, L1CSR1_ICUL - bne 3b - - icbtls 0, 0, %r9 - - sync - mfspr %r11, SPR_L1CSR1 -3: andi. %r11, %r11, L1CSR1_ICUL - bne 3b - - b 2f - .align 6 - /* Inside a locked cacheline, wait a while, write, then wait a while */ -2: sync - - mfspr %r5, TBR_TBL -4: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */ - mfspr %r5, TBR_TBL - subf. %r5, %r5, %r11 - bgt 4b - - stw %r4, 0(%r3) - - mfspr %r5, TBR_TBL -4: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */ - mfspr %r5, TBR_TBL - subf. %r5, %r5, %r11 - bgt 4b - - sync - - /* - * Fill out the rest of this cache line and the next with nops, - * to ensure that nothing outside the locked area will be - * fetched due to a branch. - */ - .rept 19 - nop - .endr - - icblc 0, 0, %r8 - icblc 0, 0, %r9 - - blr - /* * XXX: This should be moved to a shared AIM/booke asm file, if one ever is * created. Modified: head/sys/powerpc/mpc85xx/mpc85xx.c ============================================================================== --- head/sys/powerpc/mpc85xx/mpc85xx.c Tue May 1 04:06:59 2018 (r333134) +++ head/sys/powerpc/mpc85xx/mpc85xx.c Tue May 1 04:31:17 2018 (r333135) @@ -329,120 +329,6 @@ mpc85xx_is_qoriq(void) return (0); } -static void -mpc85xx_dataloss_erratum_spr976(void) -{ - uint32_t svr = SVR_VER(mfspr(SPR_SVR)); - - /* Ignore whether it's the E variant */ - svr &= ~0x8; - - if (svr != SVR_P3041 && svr != SVR_P4040 && - svr != SVR_P4080 && svr != SVR_P5020) - return; - - mb(); - isync(); - mtspr(976, (mfspr(976) & ~0x1f8) | 0x48); - isync(); -} - -static vm_offset_t -mpc85xx_map_dcsr(void) -{ - phandle_t node; - u_long b, s; - int err; - - /* - * Try to access the dcsr node directly i.e. through /aliases/. - */ - if ((node = OF_finddevice("dcsr")) != -1) - if (fdt_is_compatible_strict(node, "fsl,dcsr")) - goto moveon; - /* - * Find the node the long way. - */ - if ((node = OF_finddevice("/")) == -1) - return (0); - - if ((node = ofw_bus_find_compatible(node, "fsl,dcsr")) == 0) - return (0); - -moveon: - err = fdt_get_range(node, 0, &b, &s); - - if (err != 0) - return (0); - - law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000); - return pmap_early_io_map(b, 0x400000); -} - - - -void -mpc85xx_fix_errata(vm_offset_t va_ccsr) -{ - uint32_t svr = SVR_VER(mfspr(SPR_SVR)); - vm_offset_t va_dcsr; - - /* Ignore whether it's the E variant */ - svr &= ~0x8; - - if (svr != SVR_P3041 && svr != SVR_P4040 && - svr != SVR_P4080 && svr != SVR_P5020) - return; - - if (mfmsr() & PSL_EE) - return; - - /* - * dcsr region need to be mapped thus patch can refer to. - * Align dcsr right after ccsbar. - */ - va_dcsr = mpc85xx_map_dcsr(); - if (va_dcsr == 0) - goto err; - - /* - * As A004510 errata specify, special purpose register 976 - * SPR976[56:60] = 6'b001001 must be set. e500mc core reference manual - * does not document SPR976 register. - */ - mpc85xx_dataloss_erratum_spr976(); - - /* - * Specific settings in the CCF and core platform cache (CPC) - * are required to reconfigure the CoreNet coherency fabric. - * The register settings that should be updated are described - * in errata and relay on base address, offset and updated value. - * Special conditions must be used to update these registers correctly. - */ - dataloss_erratum_access(va_dcsr + 0xb0e08, 0xe0201800); - dataloss_erratum_access(va_dcsr + 0xb0e18, 0xe0201800); - dataloss_erratum_access(va_dcsr + 0xb0e38, 0xe0400000); - dataloss_erratum_access(va_dcsr + 0xb0008, 0x00900000); - dataloss_erratum_access(va_dcsr + 0xb0e40, 0xe00a0000); - - switch (svr) { - case SVR_P5020: - dataloss_erratum_access(va_ccsr + 0x18600, 0xc0000000); - break; - case SVR_P4040: - case SVR_P4080: - dataloss_erratum_access(va_ccsr + 0x18600, 0xff000000); - break; - case SVR_P3041: - dataloss_erratum_access(va_ccsr + 0x18600, 0xf0000000); - } - dataloss_erratum_access(va_ccsr + 0x10f00, 0x415e5000); - dataloss_erratum_access(va_ccsr + 0x11f00, 0x415e5000); - -err: - return; -} - uint32_t mpc85xx_get_platform_clock(void) { Modified: head/sys/powerpc/mpc85xx/mpc85xx.h ============================================================================== --- head/sys/powerpc/mpc85xx/mpc85xx.h Tue May 1 04:06:59 2018 (r333134) +++ head/sys/powerpc/mpc85xx/mpc85xx.h Tue May 1 04:31:17 2018 (r333135) @@ -170,8 +170,6 @@ DECLARE_CLASS(mpc85xx_platform); int mpc85xx_attach(platform_t); void mpc85xx_enable_l3_cache(void); -void mpc85xx_fix_errata(vm_offset_t); -void dataloss_erratum_access(vm_offset_t, uint32_t); int mpc85xx_is_qoriq(void); uint32_t mpc85xx_get_platform_clock(void); uint32_t mpc85xx_get_system_clock(void); Modified: head/sys/powerpc/mpc85xx/platform_mpc85xx.c ============================================================================== --- head/sys/powerpc/mpc85xx/platform_mpc85xx.c Tue May 1 04:06:59 2018 (r333134) +++ head/sys/powerpc/mpc85xx/platform_mpc85xx.c Tue May 1 04:31:17 2018 (r333135) @@ -199,9 +199,6 @@ mpc85xx_attach(platform_t plat) ccsrbar_pa = ccsrbar; ccsrbar_size = ccsrsize; -#if 0 - mpc85xx_fix_errata(ccsrbar_va); -#endif mpc85xx_enable_l3_cache(); return (0); _______________________________________________ svn-src-head@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"