Author: arybchik
Date: Mon Jan 2 09:04:22 2017
New Revision: 311056
URL: https://svnweb.freebsd.org/changeset/base/311056
Log:
MFC r310687
sfxge(4): cleanup: use TAB to indent
Found by DPDK checkpatch.sh
Sponsored by: Solarflare Communications, Inc.
Modified:
stable/10/sys/dev/sfxge/common/efx.h
stable/10/sys/dev/sfxge/common/efx_impl.h
stable/10/sys/dev/sfxge/common/efx_phy.c
stable/10/sys/dev/sfxge/common/hunt_nic.c
stable/10/sys/dev/sfxge/common/mcdi_mon.c
stable/10/sys/dev/sfxge/common/medford_nic.c
stable/10/sys/dev/sfxge/common/siena_flash.h
stable/10/sys/dev/sfxge/common/siena_impl.h
Directory Properties:
stable/10/ (props changed)
Modified: stable/10/sys/dev/sfxge/common/efx.h
==============================================================================
--- stable/10/sys/dev/sfxge/common/efx.h Mon Jan 2 09:02:39 2017
(r311055)
+++ stable/10/sys/dev/sfxge/common/efx.h Mon Jan 2 09:04:22 2017
(r311056)
@@ -847,7 +847,7 @@ typedef enum efx_phy_cap_type_e {
extern void
efx_phy_adv_cap_get(
__in efx_nic_t *enp,
- __in uint32_t flag,
+ __in uint32_t flag,
__out uint32_t *maskp);
extern __checkReturn efx_rc_t
@@ -1132,20 +1132,20 @@ typedef struct efx_nic_cfg_s {
boolean_t enc_rx_batching_enabled;
/* Maximum number of descriptors completed in an rx event. */
uint32_t enc_rx_batch_max;
- /* Number of rx descriptors the hardware requires for a push. */
- uint32_t enc_rx_push_align;
+ /* Number of rx descriptors the hardware requires for a push. */
+ uint32_t enc_rx_push_align;
/*
* Maximum number of bytes into the packet the TCP header can start for
* the hardware to apply TSO packet edits.
*/
- uint32_t enc_tx_tso_tcp_header_offset_limit;
- boolean_t enc_fw_assisted_tso_enabled;
- boolean_t enc_fw_assisted_tso_v2_enabled;
- boolean_t enc_hw_tx_insert_vlan_enabled;
+ uint32_t enc_tx_tso_tcp_header_offset_limit;
+ boolean_t enc_fw_assisted_tso_enabled;
+ boolean_t enc_fw_assisted_tso_v2_enabled;
+ boolean_t enc_hw_tx_insert_vlan_enabled;
/* Datapath firmware vadapter/vport/vswitch support */
boolean_t enc_datapath_cap_evb;
- boolean_t enc_rx_disable_scatter_supported;
- boolean_t enc_allow_set_mac_with_installed_filters;
+ boolean_t enc_rx_disable_scatter_supported;
+ boolean_t enc_allow_set_mac_with_installed_filters;
boolean_t enc_enhanced_set_mac_supported;
boolean_t enc_init_evq_v2_supported;
/* External port identifier */
@@ -1846,8 +1846,8 @@ typedef enum efx_rx_hash_support_e {
} efx_rx_hash_support_t;
#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table
*/
-#define EFX_MAXRSS 64 /* RX indirection entry range */
-#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
+#define EFX_MAXRSS 64 /* RX indirection entry range */
+#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
typedef enum efx_rx_scale_support_e {
EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
@@ -2059,7 +2059,7 @@ efx_tx_qpio_write(
__in efx_txq_t *etp,
__in_ecount(buf_length) uint8_t *buffer,
__in size_t buf_length,
- __in size_t pio_buf_offset);
+ __in size_t pio_buf_offset);
extern __checkReturn efx_rc_t
efx_tx_qpio_post(
Modified: stable/10/sys/dev/sfxge/common/efx_impl.h
==============================================================================
--- stable/10/sys/dev/sfxge/common/efx_impl.h Mon Jan 2 09:02:39 2017
(r311055)
+++ stable/10/sys/dev/sfxge/common/efx_impl.h Mon Jan 2 09:04:22 2017
(r311056)
@@ -252,7 +252,7 @@ efx_filter_reconfigure(
typedef struct efx_port_s {
efx_mac_type_t ep_mac_type;
- uint32_t ep_phy_type;
+ uint32_t ep_phy_type;
uint8_t ep_port;
uint32_t ep_mac_pdu;
uint8_t ep_mac_addr[6];
@@ -600,7 +600,7 @@ struct efx_nic_s {
uint32_t en_features;
efsys_identifier_t *en_esip;
efsys_lock_t *en_eslp;
- efsys_bar_t *en_esbp;
+ efsys_bar_t *en_esbp;
unsigned int en_mod_flags;
unsigned int en_reset_flags;
efx_nic_cfg_t en_nic_cfg;
Modified: stable/10/sys/dev/sfxge/common/efx_phy.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/efx_phy.c Mon Jan 2 09:02:39 2017
(r311055)
+++ stable/10/sys/dev/sfxge/common/efx_phy.c Mon Jan 2 09:04:22 2017
(r311056)
@@ -47,7 +47,7 @@ static const efx_phy_ops_t __efx_phy_sie
#endif /* EFSYS_OPT_PHY_STATS */
#if EFSYS_OPT_BIST
NULL, /* epo_bist_enable_offline */
- siena_phy_bist_start, /* epo_bist_start */
+ siena_phy_bist_start, /* epo_bist_start */
siena_phy_bist_poll, /* epo_bist_poll */
siena_phy_bist_stop, /* epo_bist_stop */
#endif /* EFSYS_OPT_BIST */
Modified: stable/10/sys/dev/sfxge/common/hunt_nic.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/hunt_nic.c Mon Jan 2 09:02:39 2017
(r311055)
+++ stable/10/sys/dev/sfxge/common/hunt_nic.c Mon Jan 2 09:04:22 2017
(r311056)
@@ -83,7 +83,7 @@ hunt_nic_get_required_pcie_bandwidth(
if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
&bandwidth)) != 0)
- goto fail2;
+ goto fail2;
}
out:
@@ -295,7 +295,7 @@ hunt_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
- goto fail12;
+ goto fail12;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
Modified: stable/10/sys/dev/sfxge/common/mcdi_mon.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/mcdi_mon.c Mon Jan 2 09:02:39 2017
(r311055)
+++ stable/10/sys/dev/sfxge/common/mcdi_mon.c Mon Jan 2 09:04:22 2017
(r311056)
@@ -155,8 +155,8 @@ static const struct mcdi_sensor_map_s {
STAT(Px, PHY0_VCC), /* 0x4c PHY0_VCC */
STAT(Px, PHY1_VCC), /* 0x4d PHY1_VCC */
STAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */
- STAT(Px, BOARD_FRONT_TEMP), /* 0x4f BOARD_FRONT_TEMP */
- STAT(Px, BOARD_BACK_TEMP), /* 0x50 BOARD_BACK_TEMP */
+ STAT(Px, BOARD_FRONT_TEMP), /* 0x4f BOARD_FRONT_TEMP */
+ STAT(Px, BOARD_BACK_TEMP), /* 0x50 BOARD_BACK_TEMP */
};
#define MCDI_STATIC_SENSOR_ASSERT(_field)
\
Modified: stable/10/sys/dev/sfxge/common/medford_nic.c
==============================================================================
--- stable/10/sys/dev/sfxge/common/medford_nic.c Mon Jan 2 09:02:39
2017 (r311055)
+++ stable/10/sys/dev/sfxge/common/medford_nic.c Mon Jan 2 09:04:22
2017 (r311056)
@@ -283,7 +283,7 @@ medford_board_cfg(
/* Check capabilities of running datapath firmware */
if ((rc = ef10_get_datapath_caps(enp)) != 0)
- goto fail10;
+ goto fail10;
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
Modified: stable/10/sys/dev/sfxge/common/siena_flash.h
==============================================================================
--- stable/10/sys/dev/sfxge/common/siena_flash.h Mon Jan 2 09:02:39
2017 (r311055)
+++ stable/10/sys/dev/sfxge/common/siena_flash.h Mon Jan 2 09:04:22
2017 (r311056)
@@ -127,7 +127,7 @@ typedef struct siena_mc_boot_hdr_s { /*
} siena_mc_boot_hdr_t;
#define SIENA_MC_BOOT_HDR_PADDING \
- (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t))
+ (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t))
#define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555)
#define SIENA_MC_STATIC_CONFIG_VERSION (0)
Modified: stable/10/sys/dev/sfxge/common/siena_impl.h
==============================================================================
--- stable/10/sys/dev/sfxge/common/siena_impl.h Mon Jan 2 09:02:39 2017
(r311055)
+++ stable/10/sys/dev/sfxge/common/siena_impl.h Mon Jan 2 09:04:22 2017
(r311056)
@@ -294,7 +294,7 @@ siena_vpd_fini(
typedef struct siena_link_state_s {
uint32_t sls_adv_cap_mask;
uint32_t sls_lp_cap_mask;
- unsigned int sls_fcntl;
+ unsigned int sls_fcntl;
efx_link_mode_t sls_link_mode;
#if EFSYS_OPT_LOOPBACK
efx_loopback_type_t sls_loopback;
@@ -362,7 +362,7 @@ siena_phy_bist_poll(
__in efx_bist_type_t type,
__out efx_bist_result_t *resultp,
__out_opt __drv_when(count > 0, __notnull)
- uint32_t *value_maskp,
+ uint32_t *value_maskp,
__out_ecount_opt(count) __drv_when(count > 0, __notnull)
unsigned long *valuesp,
__in size_t count);
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