Author: marius
Date: Sun Jul 5 19:33:30 2015
New Revision: 285175
URL: https://svnweb.freebsd.org/changeset/base/285175
Log:
MFC: r281751
Refine the workaround for Intel HSD131 [1] added in r269052 (MFCed to
stable/9 in r269593):
- Use the full mask described by the erratum as with a sufficiently high
number of these false-positives, the overflow bit (bit 62) additionally
gets set [7].
- HSD131 has been brought into several other Haswell-derived CPUs including
to the next generation, i. e. Intel Broadwell. Thus, also skip reporting of
these benign errors by default on CPU models affected by HSM142, HSW131 and
BDM48 [2 - 5], describing the HSD131 silicon bug for additional models.
Also, Celeron 2955U with a CPU ID of 0x45 have been reported to be covered
by this fault [6], with the specification update concerned with HSM142 [2]
only referring to 0x3c and 0x46.
Submitted by: David Froehlich [7]
Approved by: re (kib)
http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf
[1]
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf
[2]
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/5th-gen-core-family-spec-update.pdf
[3]
http://www.intel.de/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf
[4]
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v3-spec-update.pdf
[5]
https://lists.freebsd.org/pipermail/freebsd-hackers/2015-January/046878.html
[6]
Modified:
stable/9/sys/x86/x86/mca.c
Directory Properties:
stable/9/sys/ (props changed)
Modified: stable/9/sys/x86/x86/mca.c
==============================================================================
--- stable/9/sys/x86/x86/mca.c Sun Jul 5 19:32:10 2015 (r285174)
+++ stable/9/sys/x86/x86/mca.c Sun Jul 5 19:33:30 2015 (r285175)
@@ -254,15 +254,24 @@ mca_mute(const struct mca_record *rec)
{
/*
- * Skip spurious corrected parity errors generated by desktop Haswell
- * (see HSD131 erratum) unless reporting is enabled.
- * Note that these errors also have been observed with D0-stepping,
- * while the revision 014 desktop Haswell specification update only
- * talks about C0-stepping.
+ * Skip spurious corrected parity errors generated by Intel Haswell-
+ * and Broadwell-based CPUs (see HSD131, HSM142, HSW131 and BDM48
+ * erratum respectively), unless reporting is enabled.
+ * Note that these errors also have been observed with the D0-stepping
+ * of Haswell, while at least initially the CPU specification updates
+ * suggested only the C0-stepping to be affected. Similarly, Celeron
+ * 2955U with a CPU ID of 0x45 apparently are also concerned with the
+ * same problem, with HSM142 only referring to 0x3c and 0x46.
*/
- if (rec->mr_cpu_vendor_id == CPU_VENDOR_INTEL &&
- rec->mr_cpu_id == 0x306c3 && rec->mr_bank == 0 &&
- rec->mr_status == 0x90000040000f0005 && !intel6h_HSD131)
+ if (cpu_vendor_id == CPU_VENDOR_INTEL &&
+ CPUID_TO_FAMILY(cpu_id) == 0x6 &&
+ (CPUID_TO_MODEL(cpu_id) == 0x3c || /* HSD131, HSM142, HSW131 */
+ CPUID_TO_MODEL(cpu_id) == 0x3d || /* BDM48 */
+ CPUID_TO_MODEL(cpu_id) == 0x45 ||
+ CPUID_TO_MODEL(cpu_id) == 0x46) && /* HSM142 */
+ rec->mr_bank == 0 &&
+ (rec->mr_status & 0xa0000000ffffffff) == 0x80000000000f0005 &&
+ !intel6h_HSD131)
return (1);
return (0);
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