-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Aloha!
Pavel Shatov wrote: > Can one use RGMII instead of GMII? We currently have two 8-pin GPIO > headers for FPGA, this is enough for RGMII, which is only 12 pins. > Speaking of speed, Artix-7 I/O is fast enough, the only tricky thing > is that receive clock should be routed to MRCC pin (independently of > whether we use GMII or RGMII). I see no big problems with that. The RGMII interface is a bit more complex since data is clocked on both flanks to get the needed data rate. But the requirements on routing would be the same (parallel data to/from pins @ 125 MHz). If we want to be compatible with RGMII 2.0, the I/Os used in the FPGA must support HSTL. Looking at the 7Series Selecti I/O Guide this means that we need to use HP bank type for the GPIOs. And we would only support single ended HSTL. http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf So, unless we want to add even more headers on the board for the FPGA (dedicated for a possible high speed interface), being able to use existing headers is a good solution. But we should probably change from two 8-bit headers to one 16-bit header (or a single 2x8 dual row header) too more easily keep the traces aligned. In short: Changing to a single header with 16 pins, noting requirements on routing to support signalling @ 125 MHz and connecting to I/Os in the FPGA that supports HSTL should be enough at this stage to open up for a high speed interface in the future. I think that is a reasonable amount of feature creep. - -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. ======================================================================== Joachim Strömbergson Secworks AB joac...@secworks.se ======================================================================== -----BEGIN PGP SIGNATURE----- Comment: GPGTools - http://gpgtools.org Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBCAAGBQJWqHaJAAoJEF3cfFQkIuyNymwQAKOsz5xZzPkEpqKIEAij78fh m4ngXeoSz+Nd2STsHfIzTEsgXOZZxwmkHboZFhW8RQKfX6Qrzx3WpeFEe8TyDtEU 90j5Q94bpR3g8djZJhBGqFoTTBpLd4pM2ts7cqndpqAVhkaM6saL/C3+XnyqQcck dxdtBLSzZF64zFwqsUhdc5zvjftyiFh7KpPGPoB4qbi128nptiCH3T5JDQqtUjNi A7ltUarroMgjgRUeVbPEbCDWR+T8nGgr5+BMK9t17dgoCQnQtbrUhxP7x/3Kc9Wm dbpHIvOeZ9nCH+yrGjgC3eZDRt/Ir72CScOasJ2KFYOADpXn5V7PwmZbgvkU0MFB ACOTw/HcmdCLf38b4eWVdmGZJIAuX2yPBJfMCBWBI1bjTUG6iOH8spgKEo0gncms CDVMqXv90uF2sCHL79iXvPjsGLV8feDNQklkmYhtRg/0qMmuCKOB7KeSb/LpXHg+ 7A0P9vok70VgMgHT2GBJjWvip4BaUp2o67EBWHEDD/D2GQNXq8MDOQB6wu5okXgF gYSoy6wQR2SsRTq6oKklaAyaJuM8I1naNHe4bUpDJumeN12KvIRRyq8fxYOaRGLx 2ikaTp5l7e0+F0HiZWRrSvhMkodnJLx6OxWt8Yv2CPmMsFv+pOMdvaL2SsF8g4p2 YUodSc7juc0pbnUm+p9R =lZp6 -----END PGP SIGNATURE----- _______________________________________________ Tech mailing list Tech@cryptech.is https://lists.cryptech.is/listinfo/tech
