these are some "small" fixes I extracted out of the 6.2.17 driver, that
seemed somewhat safe or independent. untested.
diff -ru xf86-video-ati-newid/src/atombios_crtc.c
xf86-video-ati/src/atombios_crtc.c
--- xf86-video-ati-newid/src/atombios_crtc.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/atombios_crtc.c Sun Jan 9 12:20:16 2011
@@ -171,13 +171,13 @@
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
switch (mode) {
case DPMSModeOn:
- case DPMSModeStandby:
- case DPMSModeSuspend:
if (IS_DCE3_VARIANT)
atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id,
1);
atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
break;
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
case DPMSModeOff:
atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
diff -ru xf86-video-ati-newid/src/r600_exa.c xf86-video-ati/src/r600_exa.c
--- xf86-video-ati-newid/src/r600_exa.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/r600_exa.c Sun Jan 9 12:20:16 2011
@@ -1109,10 +1109,10 @@
accel_state->src_pitch[unit] = exaGetPixmapPitch(pPix) /
(pPix->drawable.bitsPerPixel / 8);
accel_state->src_size[unit] = exaGetPixmapPitch(pPix) *
pPix->drawable.height;
- if (accel_state->src_pitch[1] & 7)
+ if (accel_state->src_pitch[unit] & 7)
RADEON_FALLBACK(("Bad pitch %d 0x%x\n",
(int)accel_state->src_pitch[unit], unit));
- if (accel_state->src_mc_addr[1] & 0xff)
+ if (accel_state->src_mc_addr[unit] & 0xff)
RADEON_FALLBACK(("Bad offset %d 0x%x\n",
(int)accel_state->src_mc_addr[unit], unit));
for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) {
diff -ru xf86-video-ati-newid/src/r6xx_accel.c xf86-video-ati/src/r6xx_accel.c
--- xf86-video-ati-newid/src/r6xx_accel.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/r6xx_accel.c Sun Jan 9 12:20:16 2011
@@ -976,7 +976,7 @@
EREG(ib, PA_SU_POLY_OFFSET_FRONT_OFFSET, 0);
EREG(ib, PA_SU_LINE_CNTL, (8 <<
PA_SU_LINE_CNTL__WIDTH_shift)); /* Line width 1 pixel */
- EREG(ib, PA_SU_VTX_CNTL, ((2 <<
PA_SU_VTX_CNTL__ROUND_MODE_shift) |
+ EREG(ib, PA_SU_VTX_CNTL, ((2 <<
PA_SU_VTX_CNTL__ROUND_MODE_shift) | PIX_CENTER_bit |
(5 << QUANT_MODE_shift)));
/* Round to Even, fixed point 1/256 */
EREG(ib, PA_SU_POLY_OFFSET_CLAMP, 0);
diff -ru xf86-video-ati-newid/src/radeon.h xf86-video-ati/src/radeon.h
--- xf86-video-ati-newid/src/radeon.h Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon.h Sun Jan 9 12:20:16 2011
@@ -475,6 +475,9 @@
drm_handle_t fbHandle;
+ drmSize registerSize;
+ drm_handle_t registerHandle;
+
drmSize pciSize;
drm_handle_t pciMemHandle;
unsigned char *PCI; /* Map */
diff -ru xf86-video-ati-newid/src/radeon_accel.c
xf86-video-ati/src/radeon_accel.c
--- xf86-video-ati-newid/src/radeon_accel.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_accel.c Sun Jan 9 12:16:57 2011
@@ -481,12 +481,17 @@
}
}
+ /* RV410 SE cards only have 1 quadpipe */
+ if ((info->Chipset == PCI_CHIP_RV410_5E4C) ||
+ (info->Chipset == PCI_CHIP_RV410_5E4F))
+ info->accel_state->num_gb_pipes = 1;
+
if (IS_R300_3D || IS_R500_3D)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"num quad-pipes is %d\n", info->accel_state->num_gb_pipes);
if (IS_R300_3D || IS_R500_3D) {
- uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 |
R300_SUBPIXEL_1_16);
+ uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
switch(info->accel_state->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
diff -ru xf86-video-ati-newid/src/radeon_bios.c xf86-video-ati/src/radeon_bios.c
--- xf86-video-ati-newid/src/radeon_bios.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_bios.c Sun Jan 9 12:20:16 2011
@@ -273,6 +273,7 @@
unsigned char *RADEONMMIO = info->MMIO;
uint32_t reg;
+ /* first check CRTCs */
if (IS_AVIVO_VARIANT) {
reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL);
if (reg & AVIVO_CRTC_EN)
@@ -282,6 +283,15 @@
if (reg & RADEON_CRTC_EN)
return TRUE;
}
+
+ /* then check MEM_SIZE, in case something turned the crtcs off */
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ reg = INREG(R600_CONFIG_MEMSIZE);
+ else
+ reg = INREG(RADEON_CONFIG_MEMSIZE);
+
+ if (reg)
+ return TRUE;
return FALSE;
}
diff -ru xf86-video-ati-newid/src/radeon_commonfuncs.c
xf86-video-ati/src/radeon_commonfuncs.c
--- xf86-video-ati-newid/src/radeon_commonfuncs.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_commonfuncs.c Sun Jan 9 12:20:16 2011
@@ -69,7 +69,7 @@
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
- gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 |
R300_SUBPIXEL_1_16);
+ gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
switch(info->accel_state->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
diff -ru xf86-video-ati-newid/src/radeon_crtc.c xf86-video-ati/src/radeon_crtc.c
--- xf86-video-ati-newid/src/radeon_crtc.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_crtc.c Sun Jan 9 12:20:16 2011
@@ -77,6 +77,9 @@
if ((mode == DPMSModeOn) && radeon_crtc->enabled)
return;
+ if (mode == DPMSModeOff)
+ radeon_crtc_modeset_ioctl(crtc, FALSE);
+
if (IS_AVIVO_VARIANT || info->r4xx_atom) {
atombios_crtc_dpms(crtc, mode);
} else {
@@ -97,6 +100,11 @@
}
}
+ if (mode != DPMSModeOff) {
+ radeon_crtc_modeset_ioctl(crtc, TRUE);
+ radeon_crtc_load_lut(crtc);
+ }
+
if (mode == DPMSModeOn)
radeon_crtc->enabled = TRUE;
else
@@ -115,9 +123,6 @@
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- if (radeon_crtc->initialized)
- radeon_crtc_dpms(crtc, DPMSModeOff);
-
if (radeon_crtc->enabled)
crtc->funcs->hide_cursor(crtc);
}
@@ -274,7 +279,6 @@
ScrnInfoPtr pScrn = crtc->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "mode_set: x %d y %d\n", x, y);
if (IS_AVIVO_VARIANT || info->r4xx_atom) {
atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y);
} else {
@@ -287,8 +291,6 @@
{
if (crtc->scrn->pScreen != NULL)
xf86_reload_cursors(crtc->scrn->pScreen);
-
- radeon_crtc_dpms(crtc, DPMSModeOn);
}
void
diff -ru xf86-video-ati-newid/src/radeon_dri.c xf86-video-ati/src/radeon_dri.c
--- xf86-video-ati-newid/src/radeon_dri.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_dri.c Sun Jan 9 12:20:16 2011
@@ -1232,7 +1232,7 @@
drmInfo.depth_pitch = info->dri->depthPitch * drmInfo.depth_bpp /
8;
drmInfo.fb_offset = info->dri->fbHandle;
- drmInfo.mmio_offset = -1;
+ drmInfo.mmio_offset = info->dri->registerHandle;
drmInfo.ring_offset = info->dri->ringHandle;
drmInfo.ring_rptr_offset = info->dri->ringReadPtrHandle;
drmInfo.buffers_offset = info->dri->bufHandle;
@@ -1791,8 +1791,8 @@
pRADEONDRI->textureSize = info->dri->textureSize;
pRADEONDRI->log2TexGran = info->dri->log2TexGran;
- pRADEONDRI->registerHandle = -1;
- pRADEONDRI->registerSize = -1;
+ pRADEONDRI->registerHandle = info->dri->registerHandle;
+ pRADEONDRI->registerSize = info->dri->registerSize;
pRADEONDRI->statusHandle = info->dri->ringReadPtrHandle;
pRADEONDRI->statusSize = info->dri->ringReadMapSize;
diff -ru xf86-video-ati-newid/src/radeon_exa_funcs.c
xf86-video-ati/src/radeon_exa_funcs.c
--- xf86-video-ati-newid/src/radeon_exa_funcs.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_exa_funcs.c Sun Jan 9 12:16:57 2011
@@ -532,11 +532,11 @@
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Setting EXA maxPitchBytes\n");
info->accel_state->exa->maxPitchBytes = 16320;
- info->accel_state->exa->maxX = 8192;
+ info->accel_state->exa->maxX = 8191;
#else
info->accel_state->exa->maxX = 16320 / 4;
#endif
- info->accel_state->exa->maxY = 8192;
+ info->accel_state->exa->maxY = 8191;
if (xf86ReturnOptValBool(info->Options, OPTION_EXA_VSYNC, FALSE)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "EXA VSync enabled\n");
diff -ru xf86-video-ati-newid/src/radeon_exa_render.c
xf86-video-ati/src/radeon_exa_render.c
--- xf86-video-ati-newid/src/radeon_exa_render.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_exa_render.c Sun Jan 9 12:16:57 2011
@@ -409,8 +409,7 @@
RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
}
- if (repeat) {
- switch (pPict->repeatType) {
+ switch (pPict->repeatType) {
case RepeatNormal:
txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP;
break;
@@ -421,9 +420,10 @@
txfilter |= RADEON_CLAMP_S_MIRROR | RADEON_CLAMP_T_MIRROR;
break;
case RepeatNone:
- /* Nothing to do */
+ /* don't set an illegal clamp mode for rects */
+ if (txformat & RADEON_TXFORMAT_NON_POWER2)
+ txfilter |= RADEON_CLAMP_S_CLAMP_LAST |
RADEON_CLAMP_T_CLAMP_LAST;
break;
- }
}
BEGIN_ACCEL(5);
@@ -752,8 +752,7 @@
RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
}
- if (repeat) {
- switch (pPict->repeatType) {
+ switch (pPict->repeatType) {
case RepeatNormal:
txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP;
break;
@@ -764,9 +763,10 @@
txfilter |= R200_CLAMP_S_MIRROR | R200_CLAMP_T_MIRROR;
break;
case RepeatNone:
- /* Nothing to do */
+ /* don't set an illegal clamp mode for rect textures */
+ if (txformat & R200_TXFORMAT_NON_POWER2)
+ txfilter |= R200_CLAMP_S_CLAMP_LAST | R200_CLAMP_T_CLAMP_LAST;
break;
- }
}
BEGIN_ACCEL(6);
@@ -808,6 +808,10 @@
TRACE;
+ /* Check for unsupported compositing operations. */
+ if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
+ RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
+
if (!pSrcPicture->pDrawable)
RADEON_FALLBACK(("Solid or gradient pictures not supported yet\n"));
@@ -1951,8 +1955,12 @@
/* Clear out scissoring */
BEGIN_ACCEL(2);
- OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
- (0 << R300_SCISSOR_Y_SHIFT)));
+ if (IS_R300_3D)
+ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((1440 << R300_SCISSOR_X_SHIFT) |
+ (1440 << R300_SCISSOR_Y_SHIFT)));
+ else
+ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
+ (0 << R300_SCISSOR_Y_SHIFT)));
OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
(8191 << R300_SCISSOR_Y_SHIFT)));
FINISH_ACCEL();
diff -ru xf86-video-ati-newid/src/radeon_textured_videofuncs.c
xf86-video-ati/src/radeon_textured_videofuncs.c
--- xf86-video-ati-newid/src/radeon_textured_videofuncs.c Sun Jan 9
11:57:52 2011
+++ xf86-video-ati/src/radeon_textured_videofuncs.c Sun Jan 9 12:16:57 2011
@@ -2014,7 +2014,7 @@
* We render a single, large triangle and use the scissor
* functionality to restrict it to the desired rectangle.
* Due to guardband limits on r3xx/r4xx, we can only use
- * the single triangle up to 2880 pixels; above that we
+ * the single triangle up to 4021 pixels; above that we
* render as a quad.
*/
@@ -2041,7 +2041,7 @@
#endif
if (IS_R300_3D || IS_R500_3D) {
- if (IS_R300_3D && ((dstw+dsth) > 2880))
+ if (IS_R300_3D && ((dstw+dsth) > 4021))
use_quad = TRUE;
/*
* Set up the scissor area to that of the output size.
@@ -2049,10 +2049,10 @@
BEGIN_ACCEL(2);
if (IS_R300_3D) {
/* R300 has an offset */
- OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX + 1088) <<
R300_SCISSOR_X_SHIFT) |
- ((dstY + 1088) <<
R300_SCISSOR_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1088 - 1) <<
R300_SCISSOR_X_SHIFT) |
- ((dstY + dsth + 1088 - 1) <<
R300_SCISSOR_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX + 1440) <<
R300_SCISSOR_X_SHIFT) |
+ ((dstY + 1440) <<
R300_SCISSOR_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1440 - 1) <<
R300_SCISSOR_X_SHIFT) |
+ ((dstY + dsth + 1440 - 1) <<
R300_SCISSOR_Y_SHIFT)));
} else {
OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX) <<
R300_SCISSOR_X_SHIFT) |
((dstY) <<
R300_SCISSOR_Y_SHIFT)));
diff -ru xf86-video-ati-newid/src/radeon_tv.c xf86-video-ati/src/radeon_tv.c
--- xf86-video-ati-newid/src/radeon_tv.c Sun Jan 9 11:57:52 2011
+++ xf86-video-ati/src/radeon_tv.c Sun Jan 9 12:20:16 2011
@@ -640,7 +640,7 @@
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
hTotal = constPtr->horTotal;
@@ -769,7 +769,7 @@
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->tv_crc_cntl = 0;
@@ -954,10 +954,9 @@
n = PAL_TV_PLL_N_27;
p = PAL_TV_PLL_P_27;
} else {
- /* FIXME */
- m = PAL_TV_PLL_M_27;
- n = PAL_TV_PLL_N_27;
- p = PAL_TV_PLL_P_27;
+ m = PAL_TV_PLL_M_14;
+ n = PAL_TV_PLL_N_14;
+ p = PAL_TV_PLL_P_14;
}
}
save->tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) |
@@ -1095,7 +1094,7 @@
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc_h_total_disp = (((constPtr->horResolution / 8) - 1) <<
RADEON_CRTC_H_DISP_SHIFT) |
@@ -1136,7 +1135,7 @@
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl = (constPtr->horTotal & 0x7 /*0xf*/) |
RADEON_HTOT_CNTL_VGA_EN;
@@ -1199,7 +1198,7 @@
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->crtc2_h_total_disp = (((constPtr->horResolution / 8) - 1) <<
RADEON_CRTC_H_DISP_SHIFT) |
@@ -1213,7 +1212,7 @@
save->crtc2_v_total_disp = ((constPtr->verResolution - 1) <<
RADEON_CRTC_V_DISP_SHIFT) |
((constPtr->verTotal - 1) << RADEON_CRTC_V_TOTAL_SHIFT);
- save->crtc_v_sync_strt_wid = (save->crtc_v_sync_strt_wid &
~RADEON_CRTC_V_SYNC_STRT) |
+ save->crtc2_v_sync_strt_wid = (save->crtc2_v_sync_strt_wid &
~RADEON_CRTC_V_SYNC_STRT) |
((constPtr->verSyncStart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT);
}
@@ -1240,7 +1239,7 @@
if (pll->reference_freq == 2700)
constPtr = &availableTVModes[1];
else
- constPtr = &availableTVModes[1]; /* FIXME */
+ constPtr = &availableTVModes[3];
}
save->htotal_cntl2 = (constPtr->horTotal & 0x7); /* 0xf */
