See my comments inline.
Damien
| void
| -alc_aspm(struct alc_softc *sc)
| +alc_aspm(struct alc_softc *sc, int media)
| {
| uint32_t pmcfg;
| + uint16_t linkcfg;
|
| pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
| + if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
| + (ALC_FLAG_APS | ALC_FLAG_PCIE))
| + linkcfg = CSR_READ_2(sc, sc->alc_expcap +
| + PCI_PCIE_LCSR);
You should probably use pci_conf_read() here.
Just turn linkcfg into a pcireg_t.
| + else
| + linkcfg = 0;
| pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
| - pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB;
| - pmcfg |= PM_CFG_SERDES_L1_ENB;
| - pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
| + pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
| pmcfg |= PM_CFG_MAC_ASPM_CHK;
| + pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT <<
| PM_CFG_LCKDET_TIMER_SHIFT);
| + pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
| +
| + if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
| + /* Disable extended sync except AR8152 B v1.0 */
| + linkcfg &= ~0x80;
| + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
| + sc->alc_rev == ATHEROS_AR8152_B_V10)
| + linkcfg |= 0x80;
I recently added the definition of the "Extended Synch" bit to pcireg.h
so you could use PCI_PCIE_LCSR_ES instead of 0x80 here.
| + CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR,
| + linkcfg);
and use pci_conf_write() here.
| + pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
| + PM_CFG_HOTRST);
| + pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
| + PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
| + pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
| + PM_CFG_PM_REQ_TIMER_SHIFT);
| + pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
| + }
| +
| if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
| - pmcfg |= PM_CFG_SERDES_PLL_L1_ENB;
| - pmcfg &= ~PM_CFG_CLK_SWH_L1;
| - pmcfg &= ~PM_CFG_ASPM_L1_ENB;
| - pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
| + if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
| + pmcfg |= PM_CFG_ASPM_L0S_ENB;
| + if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
| + pmcfg |= PM_CFG_ASPM_L1_ENB;
| + if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
| + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
| + pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
| + pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
| + PM_CFG_SERDES_PLL_L1_ENB |
| + PM_CFG_SERDES_BUDS_RX_L1_ENB);
| + pmcfg |= PM_CFG_CLK_SWH_L1;
| + if (media == IFM_100_TX || media == IFM_1000_T) {
| + pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
| + switch (sc->sc_product) {
| + case PCI_PRODUCT_ATTANSIC_L2C_1:
| + pmcfg |= (7 <<
| + PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + break;
| + case PCI_PRODUCT_ATTANSIC_L1D_1:
| + case PCI_PRODUCT_ATTANSIC_L2C_2:
| + pmcfg |= (4 <<
| + PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + break;
| + default:
| + pmcfg |= (15 <<
| + PM_CFG_L1_ENTRY_TIMER_SHIFT);
| + break;
| + }
| + }
| + } else {
| + pmcfg |= PM_CFG_SERDES_L1_ENB |
| + PM_CFG_SERDES_PLL_L1_ENB |
| + PM_CFG_SERDES_BUDS_RX_L1_ENB;
| + pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
| + PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
| + }
| } else {
| - pmcfg &= ~PM_CFG_SERDES_PLL_L1_ENB;
| + pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
| + PM_CFG_SERDES_PLL_L1_ENB);
| pmcfg |= PM_CFG_CLK_SWH_L1;
| - pmcfg &= ~PM_CFG_ASPM_L1_ENB;
| - pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
| + if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
| + pmcfg |= PM_CFG_ASPM_L1_ENB;
| }
| CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
| }
