hello tech@
aren't these PCI_PWR_D[0-3] defines just duplicates of
PCI_PMCSR_STATE_D[0-3] from pcireg.h?
--- /usr/src/sys/dev/pci/pcivar.h.orig Sat Feb 4 01:28:05 2012
+++ /usr/src/sys/dev/pci/pcivar.h Sat Feb 4 01:28:41 2012
@@ -53,14 +53,6 @@
*/
typedef u_int32_t pcireg_t; /* configuration space register XXX */
-/*
- * Power Management (PCI 2.2)
- */
-#define PCI_PWR_D0 0
-#define PCI_PWR_D1 1
-#define PCI_PWR_D2 2
-#define PCI_PWR_D3 3
-
#ifdef _KERNEL
struct pcibus_attach_args;
--- sys/dev/pci/if_bge.c.orig Sat Feb 4 01:29:50 2012
+++ sys/dev/pci/if_bge.c Sat Feb 4 01:32:49 2012
@@ -1851,8 +1851,9 @@
* so force device into D0 state before starting initialization.
*/
pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD);
- pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
- pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
+ pm_ctl &= ~(PCI_PMCSR_STATE_D0|PCI_PMCSR_STATE_D1|
+ PCI_PMCSR_STATE_D2|PCI_PMCSR_STATE_D3);
+ pm_ctl |= (1 << 8) | PCI_PMCSR_STATE_D0; /* D0 state */
pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
DELAY(1000); /* 27 usec is allegedly sufficent */
--- sys/dev/cardbus/if_ath_cardbus.c.orig Sat Feb 4 01:36:00 2012
+++ sys/dev/cardbus/if_ath_cardbus.c Sat Feb 4 01:37:04 2012
@@ -282,7 +282,7 @@
#ifdef notyet
(void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag,
- PCI_PWR_D0);
+ PCI_PMCSR_STATE_D0);
#endif
/* Program the BAR. */
--- sys/dev/cardbus/if_atw_cardbus.c.orig Sat Feb 4 01:37:23 2012
+++ sys/dev/cardbus/if_atw_cardbus.c Sat Feb 4 01:38:07 2012
@@ -328,7 +328,7 @@
#ifdef notyet
(void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag,
- PCI_PWR_D0);
+ PCI_PMCSR_STATE_D0);
#endif
/* Program the BAR. */
