On Wed, Mar 07, 2012 at 07:20:50AM -0700, Brad Davis wrote:
> On Tue, Feb 28, 2012 at 16:43:21 +1100, Jonathan Gray wrote:
> >>This is not quite what FreeBSD has:
> >>
> >>If you look at msk_phy_power it is not just for EC_U but rather:
> >>== SK_YUKON_EC_U ||
> >>== SK_YUKON_EX ||
> >>>>= SK_YUKON_FE_P
>
> >>(linux has this as the SKY2_HW_ADV_POWER_CTL flag)
> >>
> >>additionally,
> >>
> >>OURREG5 keeps PCI_CTL_TIM_VMAIN_AV_MSK bits, not written 0
> >>setting OURREG1 to 0 missing
> >>B2_GP_IO workaround for yukon-ultra/extreme missing
>
>
> Mea Culpa, Jonathan is right because I actually took my patch from
> NetBSD (if_skreg.h 1.13 and if_msk.c 1.22). I'm sorry for the
> hassle.
So here is the diff with the changes I suggested, can you verify
this works for you as well?
Index: if_skreg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_skreg.h,v
retrieving revision 1.55
diff -u -p -r1.55 if_skreg.h
--- if_skreg.h 17 Nov 2010 13:19:39 -0000 1.55
+++ if_skreg.h 11 Mar 2012 08:10:38 -0000
@@ -465,6 +465,7 @@
#define SK_GPIO_DIR7 0x00800000
#define SK_GPIO_DIR8 0x01000000
#define SK_GPIO_DIR9 0x02000000
+#define SK_Y2_GPIO_STAT_RACE_DIS 0x2000
#define SK_Y2_CLKGATE_LINK2_INACTIVE 0x80 /* port 2 inactive */
#define SK_Y2_CLKGATE_LINK2_GATE_DIS 0x40 /* disable clock gate,
2 */
@@ -1475,11 +1476,31 @@
#define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
#define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
#define SK_PCI_PME_EVENT 0x004F
+#define SK_PCI_OURREG3 0x0080 /* Yukon EC U */
+#define SK_PCI_OURREG4 0x0084
+#define SK_PCI_OURREG5 0x0088
+#define SK_PCI_CFGREG0 0x0090
+#define SK_PCI_CFGREG1 0x0094
#define SK_Y2_REG1_PHY1_PWRD 0x04000000
#define SK_Y2_REG1_PHY2_PWRD 0x08000000
#define SK_Y2_REG1_PHY1_COMA 0x10000000
#define SK_Y2_REG1_PHY2_COMA 0x20000000
+
+/* SK_PCI_OURREG4 32bits (Yukon-ECU only) */
+#define SK_Y2_REG4_TIMER_VALUE_MSK (0xff << 16)
+#define SK_Y2_REG4_FORCE_ASPM_REQUEST 0x8000
+#define SK_Y2_REG4_ASPM_GPHY_LINK_DOWN 0x4000
+#define SK_Y2_REG4_ASPM_INT_FIFO_EMPTY 0x2000
+#define SK_Y2_REG4_ASPM_CLKRUN_REQUEST 0x1000
+#define SK_Y2_REG4_ASPM_FORCE_CLKREQ_ENA 0x10
+#define SK_Y2_REG4_ASPM_CLKREQ_PAD 0x08
+#define SK_Y2_REG4_ASPM_A1_MODE_SELECT 0x04
+#define SK_Y2_REG4_CLK_GATE_PEX_UNIT_ENA 0x02
+#define SK_Y2_REG4_CLK_GATE_ROOT_COR_ENA 0x01
+
+/* SK_PCI_OURREG5 32 bits (Yukon-ECU only) */
+#define SK_Y2_REG5_TIM_VMAIN_AV_MASK (0x03 << 27)
#define SK_PSTATE_MASK 0x0003
#define SK_PSTATE_D0 0x0000
Index: if_msk.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_msk.c,v
retrieving revision 1.93
diff -u -p -r1.93 if_msk.c
--- if_msk.c 22 Jun 2011 16:44:27 -0000 1.93
+++ if_msk.c 11 Mar 2012 08:10:39 -0000
@@ -694,6 +694,37 @@ mskc_reset(struct sk_softc *sc)
reg1 |= (SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
else
reg1 &= ~(SK_Y2_REG1_PHY1_COMA | SK_Y2_REG1_PHY2_COMA);
+
+ if (sc->sk_type == SK_YUKON_EC_U ||
+ sc->sk_type == SK_YUKON_EX ||
+ sc->sk_type >= SK_YUKON_FE_P) {
+ uint32_t our;
+ /* enable all clocks. */
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG3), 0);
+ our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4));
+ our &= (SK_Y2_REG4_FORCE_ASPM_REQUEST|
+ SK_Y2_REG4_ASPM_GPHY_LINK_DOWN|
+ SK_Y2_REG4_ASPM_INT_FIFO_EMPTY|
+ SK_Y2_REG4_ASPM_CLKRUN_REQUEST);
+ /* Set all bits to 0 except bits 15..12 */
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG4), our);
+
+ our = sk_win_read_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5));
+ our &= SK_Y2_REG5_TIM_VMAIN_AV_MASK;
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG5), our);
+ sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_CFGREG1), 0);
+
+ /*
+ * Disable status race, workaround for Yukon EC Ultra &
+ * Yukon EX.
+ */
+ our = sk_win_read_4(sc, SK_GPIO);
+ our |= SK_Y2_GPIO_STAT_RACE_DIS;
+ sk_win_write_4(sc, SK_GPIO, our);
+ sk_win_read_4(sc, SK_GPIO);
+ }
+
+ /* release PHY from PowerDown/Coma mode. */
sk_win_write_4(sc, SK_Y2_PCI_REG(SK_PCI_OURREG1), reg1);
if (sc->sk_type == SK_YUKON_XL && sc->sk_rev > SK_YUKON_XL_REV_A1)
