While the recent work in inteldrm should include
support for haswell we don't currently have the agp
parts or match on the pci devices. This diff updates
things to match on all the devices the linux driver
does with a handful of marketing names found in the
windows driver.
Compile tested only for lack of hardware to test on.
Index: pcidevs
===================================================================
RCS file: /cvs/src/sys/dev/pci/pcidevs,v
retrieving revision 1.1677
diff -u -p -r1.1677 pcidevs
--- pcidevs 28 May 2013 15:02:45 -0000 1.1677
+++ pcidevs 6 Jun 2013 07:10:51 -0000
@@ -2715,6 +2715,21 @@ product INTEL IOP333_B 0x0372 IOP333 PC
product INTEL DH89XXCC_SGMII 0x0438 DH89XXCC SGMII
product INTEL DH89XXCC_SERDES 0x043a DH89XXCC SerDes
product INTEL DH89XXCC_BPLANE 0x043c DH89XXCC backplane
+product INTEL CORE4G_D_GT1 0x0402 HD Graphics
+product INTEL CORE4G_M_GT1 0x0406 HD Graphics
+product INTEL CORE4G_S_GT1 0x040a HD Graphics
+product INTEL CORE4G_R_GT1_1 0x040b HD Graphics
+product INTEL CORE4G_R_GT1_2 0x040e HD Graphics
+product INTEL CORE4G_D_GT2 0x0412 HD Graphics 4400
+product INTEL CORE4G_M_GT2 0x0416 HD Graphics 4600
+product INTEL CORE4G_S_GT2 0x041a HD Graphics P4600
+product INTEL CORE4G_R_GT2_1 0x041b HD Graphics
+product INTEL CORE4G_R_GT2_2 0x041e HD Graphics 4600
+product INTEL CORE4G_D_GT3 0x0422 HD Graphics
+product INTEL CORE4G_M_GT2_2 0x0426 HD Graphics
+product INTEL CORE4G_S_GT3 0x042a HD Graphics
+product INTEL CORE4G_R_GT3_1 0x042b HD Graphics
+product INTEL CORE4G_R_GT3_2 0x042e HD Graphics
product INTEL DH89XXCC_SFP 0x0440 DH89XXCC SFP
product INTEL PCEB 0x0482 82375EB EISA
product INTEL CDC 0x0483 82424ZX Cache/DRAM
@@ -2733,8 +2748,53 @@ product INTEL WL_100_2 0x08af WiFi Link
product INTEL 80960RP 0x0960 i960 RP PCI-PCI
product INTEL 80960RM 0x0962 i960 RM PCI-PCI
product INTEL 80960RN 0x0964 i960 RN PCI-PCI
+product INTEL CORE4G_D_ULT_GT1 0x0a02 HD Graphics
+product INTEL CORE4G_M_ULT_GT1 0x0a06 HD Graphics
+product INTEL CORE4G_S_ULT_GT1 0x0a0a HD Graphics
+product INTEL CORE4G_R_ULT_GT1_1 0x0a0b HD Graphics
+product INTEL CORE4G_R_ULT_GT1_2 0x0a0e HD Graphics
+product INTEL CORE4G_D_ULT_GT2 0x0a12 HD Graphics
+product INTEL CORE4G_M_ULT_GT2 0x0a16 HD Graphics
+product INTEL CORE4G_S_ULT_GT2 0x0a1a HD Graphics
+product INTEL CORE4G_R_ULT_GT2_1 0x0a1b HD Graphics
+product INTEL CORE4G_R_ULT_GT2_2 0x0a1e HD Graphics
+product INTEL CORE4G_D_ULT_GT3 0x0a22 HD Graphics
+product INTEL CORE4G_M_ULT_GT3 0x0a26 HD Graphics 5000
+product INTEL CORE4G_S_ULT_GT3 0x0a2a HD Graphics
+product INTEL CORE4G_R_ULT_GT3_1 0x0a2b HD Graphics
+product INTEL CORE4G_R_ULT_GT3_2 0x0a2e Iris Graphics 5100
product INTEL D2000_IGD 0x0be1 Atom D2000/N2000 Video
product INTEL D2000_HB 0x0bf5 Atom D2000/N2000 Host
+product INTEL CORE4G_D_SDV_GT1 0x0c02 HD Graphics
+product INTEL CORE4G_M_SDV_GT1 0x0c06 HD Graphics
+product INTEL CORE4G_S_SDV_GT1 0x0c0a HD Graphics
+product INTEL CORE4G_R_SDV_GT1_1 0x0c0b HD Graphics
+product INTEL CORE4G_R_SDV_GT1_2 0x0c0e HD Graphics
+product INTEL CORE4G_D_SDV_GT2 0x0c12 HD Graphics
+product INTEL CORE4G_M_SDV_GT2 0x0c16 HD Graphics
+product INTEL CORE4G_S_SDV_GT2 0x0c1a HD Graphics
+product INTEL CORE4G_R_SDV_GT2_1 0x0c1b HD Graphics
+product INTEL CORE4G_R_SDV_GT2_2 0x0c1e HD Graphics
+product INTEL CORE4G_D_SDV_GT3 0x0c22 HD Graphics
+product INTEL CORE4G_M_SDV_GT3 0x0c26 HD Graphics
+product INTEL CORE4G_S_SDV_GT3 0x0c2a HD Graphics
+product INTEL CORE4G_R_SDV_GT3_1 0x0c2b HD Graphics
+product INTEL CORE4G_R_SDV_GT3_2 0x0c2e HD Graphics
+product INTEL CORE4G_D_CRW_GT1 0x0d02 HD Graphics
+product INTEL CORE4G_M_CRW_GT1 0x0d06 HD Graphics
+product INTEL CORE4G_S_CRW_GT1 0x0d0a HD Graphics
+product INTEL CORE4G_R_CRW_GT1_1 0x0d0b HD Graphics
+product INTEL CORE4G_R_CRW_GT1_2 0x0d0e HD Graphics
+product INTEL CORE4G_D_CRW_GT2 0x0d12 HD Graphics
+product INTEL CORE4G_M_CRW_GT2 0x0d16 HD Graphics
+product INTEL CORE4G_S_CRW_GT2 0x0d1a HD Graphics
+product INTEL CORE4G_R_CRW_GT2_1 0x0d1b HD Graphics
+product INTEL CORE4G_R_CRW_GT2_2 0x0d1e HD Graphics
+product INTEL CORE4G_D_CRW_GT3 0x0d22 Iris Pro Graphics 5200
+product INTEL CORE4G_M_CRW_GT3 0x0d26 Iris Pro Graphics 5200
+product INTEL CORE4G_S_CRW_GT3 0x0d2a HD Graphics
+product INTEL CORE4G_R_CRW_GT3_1 0x0d2b HD Graphics
+product INTEL CORE4G_R_CRW_GT3_2 0x0d2e HD Graphics
product INTEL 82542 0x1000 PRO/1000 (82542)
product INTEL 82543GC_FIBER 0x1001 PRO/1000F (82543GC)
product INTEL MODEM56 0x1002 56k Modem
Index: agp_i810.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/agp_i810.c,v
retrieving revision 1.77
diff -u -p -r1.77 agp_i810.c
--- agp_i810.c 15 May 2013 10:24:36 -0000 1.77
+++ agp_i810.c 6 Jun 2013 07:10:51 -0000
@@ -61,6 +61,7 @@
#define INTEL_COHERENT 0x6
#define GEN6_PTE_UNCACHED (1 << 1)
+#define HSW_PTE_UNCACHED (0)
#define GEN6_PTE_CACHE_LLC (2 << 1)
#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
@@ -77,6 +78,7 @@ enum {
CHIP_IRONLAKE = 9, /* Clarkdale/Arrandale */
CHIP_SANDYBRIDGE=10, /* Sandybridge */
CHIP_IVYBRIDGE =11, /* Ivybridge */
+ CHIP_HASWELL =12, /* Haswell */
};
struct agp_i810_softc {
@@ -219,6 +221,67 @@ agp_i810_get_chiptype(struct pci_attach_
case PCI_PRODUCT_INTEL_CORE3G_M_GT2:
case PCI_PRODUCT_INTEL_CORE3G_S_GT2:
return (CHIP_IVYBRIDGE);
+ case PCI_PRODUCT_INTEL_CORE4G_D_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_D_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_S_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_S_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_S_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_M_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_M_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_M_GT2_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_GT1_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_GT2_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_GT3_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_GT1_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_GT2_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_GT3_2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT1:
+ case PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT2:
+ case PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT3:
+ case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_1:
+ case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_2:
+ case PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_2:
+ return (CHIP_HASWELL);
break;
}
@@ -279,6 +342,7 @@ agp_i810_attach(struct device *parent, s
case CHIP_IRONLAKE:
case CHIP_SANDYBRIDGE:
case CHIP_IVYBRIDGE:
+ case CHIP_HASWELL:
gmaddr = AGP_I965_GMADR;
mmaddr = AGP_I965_MMADR;
memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT;
@@ -512,6 +576,7 @@ agp_i810_attach(struct device *parent, s
case CHIP_SANDYBRIDGE:
case CHIP_IVYBRIDGE:
+ case CHIP_HASWELL:
/*
* Even though stolen memory exists on these machines,
* it isn't necessarily mapped into the aperture.
@@ -580,6 +645,7 @@ agp_i810_activate(struct device *arg, in
case CHIP_IRONLAKE:
case CHIP_SANDYBRIDGE:
case CHIP_IVYBRIDGE:
+ case CHIP_HASWELL:
offset = AGP_G4X_GTT;
break;
default:
@@ -678,6 +744,15 @@ agp_i810_bind_page(void *sc, bus_addr_t
if (flags & BUS_DMA_GTT_CACHE_LLC_MLC)
physical |= GEN6_PTE_CACHE_LLC_MLC;
break;
+ case CHIP_HASWELL:
+ if (flags & BUS_DMA_GTT_NOCACHE)
+ physical |= HSW_PTE_UNCACHED;
+ if (flags & BUS_DMA_GTT_CACHE_LLC)
+ physical |= GEN6_PTE_CACHE_LLC;
+ /* Haswell doesn't set L3 this way */
+ if (flags & BUS_DMA_GTT_CACHE_LLC_MLC)
+ physical |= GEN6_PTE_CACHE_LLC;
+ break;
default:
if (flags & BUS_DMA_COHERENT)
physical |= INTEL_COHERENT;
@@ -912,6 +987,7 @@ intagp_write_gtt(struct agp_i810_softc *
/* gen6+ can do 40 bit addressing */
case CHIP_SANDYBRIDGE:
case CHIP_IVYBRIDGE:
+ case CHIP_HASWELL:
pte |= (v & 0x000000ff00000000ULL) >> 28;
break;
}
@@ -934,6 +1010,7 @@ intagp_write_gtt(struct agp_i810_softc *
case CHIP_IRONLAKE:
case CHIP_SANDYBRIDGE:
case CHIP_IVYBRIDGE:
+ case CHIP_HASWELL:
baseoff = AGP_G4X_GTT;
break;
default:
Index: drm/i915/i915_drv.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/i915/i915_drv.c,v
retrieving revision 1.31
diff -u -p -r1.31 i915_drv.c
--- drm/i915/i915_drv.c 21 May 2013 22:12:58 -0000 1.31
+++ drm/i915/i915_drv.c 6 Jun 2013 07:10:51 -0000
@@ -356,6 +356,66 @@ const static struct drm_pcidev inteldrm_
{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_D_GT2, 0 },
{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_M_GT2, 0 },
{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT3, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_1, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_2, 0 },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_2, 0 },
{0, 0, 0}
};
@@ -452,6 +512,126 @@ static const struct intel_gfx_device_id
&intel_ivybridge_m_info },
{PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE3G_S_GT2,
&intel_ivybridge_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT1, /* GT1 desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT2, /* GT2 desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_GT3, /* GT3 desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT1, /* GT1 server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT2, /* GT2 server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_GT3, /* GT3 server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT1, /* GT1 mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2, /* GT2 mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_GT2_2, /* GT2 mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_1, /* GT1 reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_1, /* GT2 reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_1, /* GT3 reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT1_2, /* GT1 reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT2_2, /* GT2 reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_GT3_2, /* GT3 reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT1, /* SDV GT1
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT2, /* SDV GT2
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_SDV_GT3, /* SDV GT3
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT1, /* SDV GT1
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT2, /* SDV GT2
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_SDV_GT3, /* SDV GT3
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT1, /* SDV GT1
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT2, /* SDV GT2
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_SDV_GT3, /* SDV GT3
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_1, /* SDV GT1
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_1, /* SDV GT2
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_1, /* SDV GT3
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT1_2, /* SDV GT1
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT2_2, /* SDV GT2
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_SDV_GT3_2, /* SDV GT3
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT1, /* ULT GT1
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT2, /* ULT GT2
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_ULT_GT3, /* ULT GT3
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT1, /* ULT GT1
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT2, /* ULT GT2
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_ULT_GT3, /* ULT GT3
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT1, /* ULT GT1
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT2, /* ULT GT2
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_ULT_GT3, /* ULT GT3
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_1, /* ULT GT1
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_1, /* ULT GT2
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_1, /* ULT GT3
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT1_2, /* ULT GT1
reserved */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT2_2, /* ULT GT2
reserved */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_ULT_GT3_2, /* ULT GT3
reserved */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT1, /* CRW GT1
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT2, /* CRW GT2
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_D_CRW_GT3, /* CRW GT3
desktop */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT1, /* CRW GT1
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT2, /* CRW GT2
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_S_CRW_GT3, /* CRW GT3
server */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT1, /* CRW GT1
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT2, /* CRW GT2
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_M_CRW_GT3, /* CRW GT3
mobile */
+ &intel_haswell_m_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_1, /* CRW GT1
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_1, /* CRW GT2
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_1, /* CRW GT3
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT1_2, /* CRW GT1
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT2_2, /* CRW GT2
reserved */
+ &intel_haswell_d_info },
+ {PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CORE4G_R_CRW_GT3_2, /* CRW GT3
reserved */
+ &intel_haswell_d_info },
{0, 0, NULL}
};
