Here's the rest of the changes required to get ethernet working on the
edgerouter lite, which makes it possible to boot off nfsroot and do exciting
stuff like build kernels.
- add atphy(4) to configs
- allow separate rx and tx clock settings
- add phy mapping for erl
- add tx/rx clock settings for erl
ok?
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
Copyright (c) 1995-2013 OpenBSD. All rights reserved. http://www.OpenBSD.org
OpenBSD 5.4-current (GENERIC) #29: Tue Sep 17 08:07:14 EST 2013
r...@cantrip.eait.uq.edu.au:/usr/src/sys/arch/octeon/compile/GENERIC
real mem = 247922688 (236MB)
avail mem = 245612544 (234MB)
mainbus0 at root
cpu0 at mainbus0: Cavium OCTEON CPU rev 0.1 500 MHz, Software FP emulation
cpu0: cache L1-I 32KB D 16KB 4 way, L2 128KB direct
clock0 at mainbus0: int 5
iobus0 at mainbus0
octcf at iobus0 base 0x1d000800 irq 0 not configured
pcibus at iobus0 irq 0 not configured
cn30xxgmx0 at iobus0 base 0x1180008000000 irq 48
cnmac0 at cn30xxgmx0 address=0x0001180008000000: RGMII, address
dc:9f:db:29:40:2f
atphy0 at cnmac0 phy 7: F1 10/100/1000 PHY, rev. 2
cnmac1 at cn30xxgmx0 address=0x0001180008000000: RGMII, address
dc:9f:db:29:40:30
atphy1 at cnmac1 phy 6: F1 10/100/1000 PHY, rev. 2
cnmac2 at cn30xxgmx0 address=0x0001180008000000: RGMII, address
dc:9f:db:29:40:31
atphy2 at cnmac2 phy 5: F1 10/100/1000 PHY, rev. 2
uar: ns16550, no working fifo
com0: console
com1 at uartbus0 base 0x1180000000c00 irq 35: ns16550, no working fifo
/dev/ksyms: Symbol table not valid.
vscsi0 at root
scsibus0 at vscsi0: 256 targets
softraid0 at root
scsibus1 at softraid0: 256 targets
root device: cnmac0
nfs_boot: using interface cnmac0, with revarp & bootparams
cnmac0: link up (1000baseT-FDX)
cnmac0: link down
cnmac0: link up (1000baseT-FDX)
nfs_boot: client_addr=192.168.1.2
nfs_boot: server_addr=192.168.1.22 hostname=erl
root on 192.168.1.22:/srv/octeon-nfsroot
WARNING: No TOD clock, believing file system.
WARNING: CHECK AND RESET THE DATE!
swap on 192.168.1.22:/srv/octeon-nfsswap
Index: arch/octeon/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/octeon/conf/GENERIC,v
retrieving revision 1.9
diff -u -p -r1.9 GENERIC
--- arch/octeon/conf/GENERIC 24 Jun 2011 02:18:17 -0000 1.9
+++ arch/octeon/conf/GENERIC 16 Sep 2013 22:50:31 -0000
@@ -44,6 +44,7 @@ cnmac* at cn30xxgmx?
rgephy* at mii?
ukphy* at mii?
+atphy* at mii?
# IDE Controller
pciide* at pci? flags 0x0000
Index: arch/octeon/conf/RAMDISK
===================================================================
RCS file: /cvs/src/sys/arch/octeon/conf/RAMDISK,v
retrieving revision 1.11
diff -u -p -r1.11 RAMDISK
--- arch/octeon/conf/RAMDISK 26 Mar 2013 14:23:19 -0000 1.11
+++ arch/octeon/conf/RAMDISK 16 Sep 2013 22:50:31 -0000
@@ -64,6 +64,7 @@ cnmac* at cn30xxgmx?
rgephy* at mii?
ukphy* at mii?
+atphy* at mii?
pseudo-device loop 1 # network loopback
pseudo-device bpfilter 1 # packet filter
Index: arch/octeon/dev/cn30xxasx.c
===================================================================
RCS file: /cvs/src/sys/arch/octeon/dev/cn30xxasx.c,v
retrieving revision 1.3
diff -u -p -r1.3 cn30xxasx.c
--- arch/octeon/dev/cn30xxasx.c 5 Dec 2012 23:20:14 -0000 1.3
+++ arch/octeon/dev/cn30xxasx.c 16 Sep 2013 22:50:31 -0000
@@ -175,10 +175,10 @@ cn30xxasx_enable_intr(struct cn30xxasx_s
#endif
int
-cn30xxasx_clk_set(struct cn30xxasx_softc *sc, int setting)
+cn30xxasx_clk_set(struct cn30xxasx_softc *sc, int tx_setting, int rx_setting)
{
- _ASX_WR8(sc, ASX0_TX_CLK_SET0_OFFSET + 8 * sc->sc_port, setting);
- _ASX_WR8(sc, ASX0_RX_CLK_SET0_OFFSET + 8 * sc->sc_port, setting);
+ _ASX_WR8(sc, ASX0_TX_CLK_SET0_OFFSET + 8 * sc->sc_port, tx_setting);
+ _ASX_WR8(sc, ASX0_RX_CLK_SET0_OFFSET + 8 * sc->sc_port, rx_setting);
return 0;
}
Index: arch/octeon/dev/cn30xxasxvar.h
===================================================================
RCS file: /cvs/src/sys/arch/octeon/dev/cn30xxasxvar.h,v
retrieving revision 1.1
diff -u -p -r1.1 cn30xxasxvar.h
--- arch/octeon/dev/cn30xxasxvar.h 16 Jun 2011 11:22:30 -0000 1.1
+++ arch/octeon/dev/cn30xxasxvar.h 16 Sep 2013 22:50:31 -0000
@@ -50,7 +50,7 @@ struct cn30xxasx_attach_args {
void cn30xxasx_init(struct cn30xxasx_attach_args *,
struct cn30xxasx_softc **);
int cn30xxasx_enable(struct cn30xxasx_softc *, int);
-int cn30xxasx_clk_set(struct cn30xxasx_softc *, int);
+int cn30xxasx_clk_set(struct cn30xxasx_softc *, int, int);
uint64_t cn30xxasx_int_summary(struct cn30xxasx_softc *sc);
#endif
Index: arch/octeon/dev/cn30xxgmx.c
===================================================================
RCS file: /cvs/src/sys/arch/octeon/dev/cn30xxgmx.c,v
retrieving revision 1.6
diff -u -p -r1.6 cn30xxgmx.c
--- arch/octeon/dev/cn30xxgmx.c 16 Sep 2013 20:52:13 -0000 1.6
+++ arch/octeon/dev/cn30xxgmx.c 16 Sep 2013 22:50:31 -0000
@@ -41,6 +41,7 @@
#include <machine/bus.h>
#include <machine/octeon_model.h>
+#include <machine/octeonvar.h>
#include <octeon/dev/iobusvar.h>
#include <octeon/dev/cn30xxciureg.h>
@@ -190,9 +191,19 @@ cn30xxgmx_match(struct device *parent, v
static int
cn30xxgmx_port_phy_addr(int port)
{
- if (port >= nitems(octeon_eth_phy_table))
- return -1;
- return octeon_eth_phy_table[port];
+ extern struct boot_info *octeon_boot_info;
+
+ switch (octeon_boot_info->board_type) {
+ case BOARD_TYPE_UBIQUITI_E100:
+ if (port > 2)
+ return -1;
+ return 7 - port;
+
+ default:
+ if (port >= nitems(octeon_eth_phy_table))
+ return -1;
+ return octeon_eth_phy_table[port];
+ }
}
static void
@@ -977,7 +988,9 @@ cn30xxgmx_rgmii_speed_speed(struct cn30x
static int
cn30xxgmx_rgmii_timing(struct cn30xxgmx_port_softc *sc)
{
- int clk_set_setting;
+ extern struct boot_info *octeon_boot_info;
+ int clk_tx_setting;
+ int clk_rx_setting;
uint64_t rx_frm_ctl;
/* RGMII TX Threshold Registers, CN30XX-HM-1.0;
@@ -1022,15 +1035,25 @@ cn30xxgmx_rgmii_timing(struct cn30xxgmx_
/*
* Table.4-6, Summary of ASX Registers, SEIL_HS_v03;
*/
- clk_set_setting = 0;
+ clk_tx_setting = 0;
+ clk_rx_setting = 0;
break;
default:
/* Default parameter of CN30XX */
- clk_set_setting = 24;
+ clk_tx_setting = 24;
+ clk_rx_setting = 24;
+ break;
+ }
+
+ /* board specific overrides */
+ switch (octeon_boot_info->board_type) {
+ case BOARD_TYPE_UBIQUITI_E100:
+ clk_tx_setting = 16;
+ clk_rx_setting = 0;
break;
}
- cn30xxasx_clk_set(sc->sc_port_asx, clk_set_setting);
+ cn30xxasx_clk_set(sc->sc_port_asx, clk_tx_setting, clk_rx_setting);
return 0;
}
