On Tue, Oct 01, 2013 at 09:32:30PM +0200, Mark Kettenis wrote: > Some re(4) variants now use msi. Unfortunately the interrupt handler > isn't careful enough, and we might miss an interrupt. The diff below > seems to fix that by disabling the interrupts while processing an > interrupt. This is what FreeBSD & Linux seem to do. > > Needs testing on a wide variety of re(4), especially on thoe that > don't use msi yet. > > > Index: re.c > =================================================================== > RCS file: /cvs/src/sys/dev/ic/re.c,v > retrieving revision 1.143 > diff -u -p -r1.143 re.c > --- re.c 7 Aug 2013 01:06:30 -0000 1.143 > +++ re.c 21 Aug 2013 19:50:39 -0000 > @@ -1650,6 +1650,9 @@ re_intr(void *arg) > if (!(ifp->if_flags & IFF_RUNNING)) > return (0); > > + /* Disable interrupts. */ > + CSR_WRITE_2(sc, RL_IMR, 0); > + > rx = tx = 0; > status = CSR_READ_2(sc, RL_ISR); > /* If the card has gone away the read returns 0xffff. */ > @@ -1715,6 +1718,8 @@ re_intr(void *arg) > > if (tx && !IFQ_IS_EMPTY(&ifp->if_snd)) > re_start(ifp); > + > + CSR_WRITE_2(sc, RL_IMR, sc->rl_intrs); > > return (claimed); > } >
Also working fine on amd64 with re0 at pci3 dev 0 function 0 "Realtek 8101E" rev 0x02: RTL8102EL (0x2480), msi, address 3c:4a:92:54:1b:cf rlphy0 at re0 phy 7: RTL8201L 10/100 PHY, rev. 1 In this case the diff seems to have significantly improved performance and latency. .... Ken
