This adds the initial bits for the i217/i218 PHY and the
Lynx Point PCH found in Haswell systems.
Doesn't include the new workarounds yet and follows
the pch2/82579 paths for now but this seems to be enough
to make a desktop machine with I217-LM work
Index: if_em.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_em.c,v
retrieving revision 1.270
diff -u -p -r1.270 if_em.c
--- if_em.c 19 Oct 2013 15:45:33 -0000 1.270
+++ if_em.c 9 Nov 2013 01:30:38 -0000
@@ -130,6 +130,10 @@ const struct pci_matchid em_devices[] =
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES },
@@ -794,6 +798,7 @@ em_init(void *arg)
break;
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
pba = E1000_PBA_26K;
break;
default:
@@ -1632,7 +1637,8 @@ em_allocate_pci_resources(struct em_soft
sc->hw.mac_type == em_ich9lan ||
sc->hw.mac_type == em_ich10lan ||
sc->hw.mac_type == em_pchlan ||
- sc->hw.mac_type == em_pch2lan) {
+ sc->hw.mac_type == em_pch2lan ||
+ sc->hw.mac_type == em_pch_lpt) {
val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_FLASH);
if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
printf(": flash is not mem space\n");
Index: if_em_hw.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_em_hw.c,v
retrieving revision 1.73
diff -u -p -r1.73 if_em_hw.c
--- if_em_hw.c 7 Aug 2013 01:06:34 -0000 1.73
+++ if_em_hw.c 9 Nov 2013 01:30:38 -0000
@@ -255,6 +255,9 @@ em_set_phy_type(struct em_hw *hw)
case I82579_E_PHY_ID:
hw->phy_type = em_phy_82579;
break;
+ case I217_E_PHY_ID:
+ hw->phy_type = em_phy_i217;
+ break;
case I82580_I_PHY_ID:
case I350_I_PHY_ID:
hw->phy_type = em_phy_82580;
@@ -568,6 +571,12 @@ em_set_mac_type(struct em_hw *hw)
case E1000_DEV_ID_PCH2_LV_V:
hw->mac_type = em_pch2lan;
break;
+ case E1000_DEV_ID_PCH_LPT_I217_LM:
+ case E1000_DEV_ID_PCH_LPT_I217_V:
+ case E1000_DEV_ID_PCH_LPTLP_I218_LM:
+ case E1000_DEV_ID_PCH_LPTLP_I218_V:
+ hw->mac_type = em_pch_lpt;
+ break;
case E1000_DEV_ID_EP80579_LAN_1:
hw->mac_type = em_icp_xxxx;
hw->icp_xxxx_port_num = 0;
@@ -591,6 +600,7 @@ em_set_mac_type(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
hw->swfwhw_semaphore_present = TRUE;
hw->asf_firmware_present = TRUE;
break;
@@ -682,6 +692,7 @@ em_set_media_type(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
case em_82573:
case em_82574:
/*
@@ -838,6 +849,7 @@ em_reset_hw(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
if (!hw->phy_reset_disable &&
em_check_phy_reset_block(hw) == E1000_SUCCESS) {
/*
@@ -850,7 +862,7 @@ em_reset_hw(struct em_hw *hw)
* Gate automatic PHY configuration by hardware on
* non-managed 82579
*/
- if ((hw->mac_type == em_pch2lan) &&
+ if ((hw->mac_type == em_pch2lan || hw->mac_type ==
em_pch_lpt) &&
!(E1000_READ_REG(hw, FWSM) &
E1000_FWSM_FW_VALID)) {
em_gate_hw_phy_config_ich8lan(hw, TRUE);
}
@@ -860,7 +872,8 @@ em_reset_hw(struct em_hw *hw)
msec_delay(5);
/* Ungate automatic PHY configuration on non-managed 82579 */
- if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable &&
+ if ((hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt)
&&
+ !hw->phy_reset_disable &&
!(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
msec_delay(10);
em_gate_hw_phy_config_ich8lan(hw, FALSE);
@@ -973,7 +986,8 @@ em_reset_hw(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
uint32_t kab = E1000_READ_REG(hw, KABGTXD);
kab |= E1000_KABGTXD_BGSQLBIAS;
E1000_WRITE_REG(hw, KABGTXD, kab);
@@ -1089,6 +1103,7 @@ em_initialize_hardware_bits(struct em_hw
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
if (hw->mac_type == em_ich8lan)
/* Set TARC0 bits 29 and 28 */
reg_tarc0 |= 0x30000000;
@@ -1162,7 +1177,8 @@ em_init_hw(struct em_hw *hw)
}
if (hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/*
* The MAC-PHY interconnect may still be in SMBus mode
* after Sx->S0. Toggle the LANPHYPC Value bit to force
@@ -1182,7 +1198,7 @@ em_init_hw(struct em_hw *hw)
}
/* Gate automatic PHY configuration on non-managed 82579 */
- if (hw->mac_type == em_pch2lan)
+ if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt)
em_gate_hw_phy_config_ich8lan(hw, TRUE);
/*
@@ -1195,7 +1211,7 @@ em_init_hw(struct em_hw *hw)
em_phy_reset(hw);
/* Ungate automatic PHY configuration on non-managed 82579 */
- if (hw->mac_type == em_pch2lan &&
+ if ((hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt)
&&
(fwsm & E1000_FWSM_FW_VALID) == 0)
em_gate_hw_phy_config_ich8lan(hw, FALSE);
@@ -1224,7 +1240,8 @@ em_init_hw(struct em_hw *hw)
hw->mac_type != em_ich9lan &&
hw->mac_type != em_ich10lan &&
hw->mac_type != em_pchlan &&
- hw->mac_type != em_pch2lan) {
+ hw->mac_type != em_pch2lan &&
+ hw->mac_type != em_pch_lpt) {
if (hw->mac_type < em_82545_rev_3)
E1000_WRITE_REG(hw, VET, 0);
if (hw->mac_type == em_i350)
@@ -1261,7 +1278,8 @@ em_init_hw(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
for (i = 0; i < mta_size; i++) {
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
@@ -1319,7 +1337,8 @@ em_init_hw(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
msec_delay(15);
/*
@@ -1383,6 +1402,7 @@ em_init_hw(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
ctrl = E1000_READ_REG(hw, TXDCTL1);
ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
E1000_TXDCTL_FULL_TX_DESC_WB;
@@ -1410,7 +1430,8 @@ em_init_hw(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
if (hw->mac_type == em_ich8lan)
snoop = PCI_EX_82566_SNOOP_ALL;
else
@@ -1517,6 +1538,7 @@ em_setup_link(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
case em_82573:
case em_82574:
hw->fc = E1000_FC_FULL;
@@ -1609,7 +1631,8 @@ em_setup_link(struct em_hw *hw)
hw->mac_type != em_ich9lan &&
hw->mac_type != em_ich10lan &&
hw->mac_type != em_pchlan &&
- hw->mac_type != em_pch2lan) {
+ hw->mac_type != em_pch2lan &&
+ hw->mac_type != em_pch_lpt) {
E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
@@ -1618,7 +1641,8 @@ em_setup_link(struct em_hw *hw)
if (hw->phy_type == em_phy_82577 ||
hw->phy_type == em_phy_82578 ||
- hw->phy_type == em_phy_82579) {
+ hw->phy_type == em_phy_82579 ||
+ hw->phy_type == em_phy_i217) {
E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000);
em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
hw->fc_pause_time);
@@ -1969,7 +1993,8 @@ em_copper_link_igp_setup(struct em_hw *h
}
/* disable lplu d0 during driver init */
if (hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
ret_val = em_set_lplu_state_pchlan(hw, FALSE);
else
ret_val = em_set_d0_lplu_state(hw, FALSE);
@@ -2240,7 +2265,8 @@ em_copper_link_mgp_setup(struct em_hw *h
/* disable lplu d0 during driver init */
if (hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
ret_val = em_set_lplu_state_pchlan(hw, FALSE);
/* Enable CRS on TX. This must be set for half-duplex operation. */
@@ -2582,6 +2608,7 @@ em_setup_copper_link(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
/*
* Set the mac to wait the maximum time between each
* iteration and increase the max iterations when polling the
@@ -2641,7 +2668,8 @@ em_setup_copper_link(struct em_hw *hw)
if (ret_val)
return ret_val;
} else if (hw->phy_type == em_phy_82577 ||
- hw->phy_type == em_phy_82579) {
+ hw->phy_type == em_phy_82579 ||
+ hw->phy_type == em_phy_i217) {
ret_val = em_copper_link_82577_setup(hw);
if (ret_val)
return ret_val;
@@ -3692,7 +3720,8 @@ em_check_for_link(struct em_hw *hw)
em_check_downshift(hw);
/* Enable/Disable EEE after link up */
- if (hw->mac_type == em_pch2lan) {
+ if (hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
ret_val = em_set_eee_pchlan(hw);
if (ret_val)
return ret_val;
@@ -4476,7 +4505,8 @@ em_read_phy_reg(struct em_hw *hw, uint32
DEBUGFUNC("em_read_phy_reg");
if (hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE));
if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) &&
@@ -4589,7 +4619,7 @@ em_read_phy_reg_ex(struct em_hw *hw, uin
}
*phy_data = (uint16_t) mdic;
- if (hw->mac_type == em_pch2lan)
+ if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt)
usec_delay(100);
} else {
/*
@@ -4639,7 +4669,8 @@ em_write_phy_reg(struct em_hw *hw, uint3
DEBUGFUNC("em_write_phy_reg");
if (hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE));
if (em_swfw_sync_acquire(hw, hw->swfw))
@@ -4739,7 +4770,7 @@ em_write_phy_reg_ex(struct em_hw *hw, ui
return -E1000_ERR_PHY;
}
- if (hw->mac_type == em_pch2lan)
+ if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt)
usec_delay(100);
} else {
/*
@@ -4918,14 +4949,14 @@ em_oem_bits_config_pchlan(struct em_hw *
uint16_t oem_reg;
uint16_t swfw = E1000_SWFW_PHY0_SM;
- if ((hw->mac_type != em_pchlan) && (hw->mac_type != em_pch2lan))
+ if (hw->mac_type < em_pchlan)
return ret_val;
ret_val = em_swfw_sync_acquire(hw, swfw);
if (ret_val)
return ret_val;
- if (hw->mac_type != em_pch2lan) {
+ if (hw->mac_type == em_pchlan) {
mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL);
if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
goto out;
@@ -5215,6 +5246,10 @@ em_match_gig_phy(struct em_hw *hw)
if (hw->phy_id == I82579_E_PHY_ID)
match = TRUE;
break;
+ case em_pch_lpt:
+ if (hw->phy_id == I217_E_PHY_ID)
+ match = TRUE;
+ break;
case em_icp_xxxx:
if (hw->phy_id == M88E1141_E_PHY_ID)
match = TRUE;
@@ -5495,6 +5530,7 @@ em_init_eeprom_params(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
{
int32_t i = 0;
uint32_t flash_size =
@@ -6119,7 +6155,8 @@ em_is_onboard_nvm_eeprom(struct em_hw *h
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
return FALSE;
if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
@@ -6184,7 +6221,8 @@ em_validate_eeprom_checksum(struct em_hw
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/*
* Drivers must allocate the shadow ram structure for the
* EEPROM checksum to be updated. Otherwise, this bit as
@@ -6771,7 +6809,8 @@ em_init_rx_addrs(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
rar_num = E1000_RAR_ENTRIES_ICH8LAN;
if (hw->mac_type == em_ich8lan)
rar_num -= 1;
@@ -6826,7 +6865,8 @@ em_mc_addr_list_update(struct em_hw *hw,
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
if (hw->mac_type == em_ich8lan)
num_rar_entry -= 1;
@@ -6852,7 +6892,8 @@ em_mc_addr_list_update(struct em_hw *hw,
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
for (i = 0; i < num_mta_entry; i++) {
@@ -6915,7 +6956,8 @@ em_hash_mc_addr(struct em_hw *hw, uint8_
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/* [47:38] i.e. 0x158 for above example address */
hash_value = ((mc_addr[4] >> 6) |
(((uint16_t) mc_addr[5]) << 2));
@@ -6930,7 +6972,8 @@ em_hash_mc_addr(struct em_hw *hw, uint8_
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/* [46:37] i.e. 0x2B1 for above example address */
hash_value = ((mc_addr[4] >> 5) |
(((uint16_t) mc_addr[5]) << 3));
@@ -6945,7 +6988,8 @@ em_hash_mc_addr(struct em_hw *hw, uint8_
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/* [45:36] i.e. 0x163 for above example address */
hash_value = ((mc_addr[4] >> 4) |
(((uint16_t) mc_addr[5]) << 4));
@@ -6960,7 +7004,8 @@ em_hash_mc_addr(struct em_hw *hw, uint8_
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/* [43:34] i.e. 0x18D for above example address */
hash_value = ((mc_addr[4] >> 2) |
(((uint16_t) mc_addr[5]) << 6));
@@ -6977,7 +7022,8 @@ em_hash_mc_addr(struct em_hw *hw, uint8_
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
hash_value &= 0x3FF;
return hash_value;
@@ -7009,7 +7055,8 @@ em_mta_set(struct em_hw *hw, uint32_t ha
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
hash_reg &= 0x1F;
hash_bit = hash_value & 0x1F;
@@ -7104,7 +7151,8 @@ em_clear_vfta(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
return;
if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
@@ -7259,7 +7307,8 @@ em_clear_hw_cntrs(struct em_hw *hw)
hw->mac_type != em_ich9lan &&
hw->mac_type != em_ich10lan &&
hw->mac_type != em_pchlan &&
- hw->mac_type != em_pch2lan) {
+ hw->mac_type != em_pch2lan &&
+ hw->mac_type != em_pch_lpt) {
temp = E1000_READ_REG(hw, PRC64);
temp = E1000_READ_REG(hw, PRC127);
temp = E1000_READ_REG(hw, PRC255);
@@ -7291,7 +7340,8 @@ em_clear_hw_cntrs(struct em_hw *hw)
hw->mac_type != em_ich9lan &&
hw->mac_type != em_ich10lan &&
hw->mac_type != em_pchlan &&
- hw->mac_type != em_pch2lan) {
+ hw->mac_type != em_pch2lan &&
+ hw->mac_type != em_pch_lpt) {
temp = E1000_READ_REG(hw, PTC64);
temp = E1000_READ_REG(hw, PTC127);
temp = E1000_READ_REG(hw, PTC255);
@@ -7328,7 +7378,8 @@ em_clear_hw_cntrs(struct em_hw *hw)
if (hw->phy_type == em_phy_82577 ||
hw->phy_type == em_phy_82578 ||
- hw->phy_type == em_phy_82579) {
+ hw->phy_type == em_phy_82579 ||
+ hw->phy_type == em_phy_i217) {
uint16_t phy_data;
em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
@@ -7351,7 +7402,7 @@ em_clear_hw_cntrs(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type != em_pch2lan)
+ (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt))
return;
temp = E1000_READ_REG(hw, ICRXPTC);
@@ -7491,6 +7542,7 @@ em_get_bus_info(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
hw->bus_type = em_bus_type_pci_express;
hw->bus_speed = em_bus_speed_2500;
hw->bus_width = em_bus_width_pciex_1;
@@ -8066,7 +8118,8 @@ em_set_d3_lplu_state(struct em_hw *hw, b
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
/*
* MAC writes into PHY register based on the state transition
* and start auto-negotiation. SW driver can overwrite the
@@ -8093,7 +8146,8 @@ em_set_d3_lplu_state(struct em_hw *hw, b
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
@@ -8149,7 +8203,8 @@ em_set_d3_lplu_state(struct em_hw *hw, b
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
@@ -8205,7 +8260,8 @@ em_set_d0_lplu_state(struct em_hw *hw, b
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
} else {
ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
@@ -8219,7 +8275,8 @@ em_set_d0_lplu_state(struct em_hw *hw, b
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
@@ -8263,7 +8320,8 @@ em_set_d0_lplu_state(struct em_hw *hw, b
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
@@ -8456,7 +8514,8 @@ em_check_mng_mode(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
return TRUE;
@@ -8705,6 +8764,7 @@ em_get_auto_rd_done(struct em_hw *hw)
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
+ case em_pch_lpt:
while (timeout) {
if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
break;
@@ -8944,7 +9004,8 @@ em_check_phy_reset_block(struct em_hw *h
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
fwsm = E1000_READ_REG(hw, FWSM);
return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS :
E1000_BLK_PHY_RESET;
@@ -8986,7 +9047,8 @@ em_set_pci_ex_no_snoop(struct em_hw *hw,
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
uint32_t ctrl_ext;
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
@@ -9015,7 +9077,8 @@ em_get_software_flag(struct em_hw *hw)
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
while (timeout) {
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
@@ -9055,7 +9118,8 @@ em_release_software_flag(struct em_hw *h
hw->mac_type == em_ich9lan ||
hw->mac_type == em_ich10lan ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan) {
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt) {
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
@@ -9744,7 +9808,8 @@ em_init_lcd_from_nvm(struct em_hw *hw)
if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT ||
hw->device_id == E1000_DEV_ID_ICH8_IGP_M ||
hw->mac_type == em_pchlan ||
- hw->mac_type == em_pch2lan)
+ hw->mac_type == em_pch2lan ||
+ hw->mac_type == em_pch_lpt)
sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
else
sw_cfg_mask = FEXTNVM_SW_CONFIG;
@@ -10169,7 +10234,7 @@ em_gate_hw_phy_config_ich8lan(struct em_
DEBUGFUNC("em_gate_hw_phy_config_ich8lan");
- if (hw->mac_type != em_pch2lan)
+ if (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt)
return;
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
@@ -10244,7 +10309,7 @@ em_lv_phy_workarounds_ich8lan(struct em_
DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
- if (hw->mac_type != em_pch2lan)
+ if (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt)
goto out;
/* Set MDIO slow mode before any other MDIO access */
@@ -10321,7 +10386,8 @@ em_set_eee_pchlan(struct em_hw *hw)
DEBUGFUNC("em_set_eee_pchlan");
- if (hw->phy_type != em_phy_82579)
+ if (hw->phy_type != em_phy_82579 &&
+ hw->phy_type != em_phy_i217)
goto out;
ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg);
Index: if_em_hw.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_em_hw.h,v
retrieving revision 1.54
diff -u -p -r1.54 if_em_hw.h
--- if_em_hw.h 26 Nov 2012 01:17:41 -0000 1.54
+++ if_em_hw.h 9 Nov 2013 01:30:38 -0000
@@ -78,6 +78,7 @@ typedef enum {
em_ich10lan,
em_pchlan,
em_pch2lan,
+ em_pch_lpt,
em_num_macs
} em_mac_type;
@@ -242,6 +243,7 @@ typedef enum {
em_phy_82577,
em_phy_82578,
em_phy_82579,
+ em_phy_i217,
em_phy_82580,
em_phy_undefined = 0xFF
} em_phy_type;
@@ -536,6 +538,10 @@ int32_t em_check_phy_reset_block(struct
#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
#define E1000_DEV_ID_PCH2_LV_LM 0x1502
#define E1000_DEV_ID_PCH2_LV_V 0x1503
+#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
+#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
+#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
+#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
#define E1000_DEV_ID_82575EB_PT 0x10A7
#define E1000_DEV_ID_82575EB_PF 0x10A9
#define E1000_DEV_ID_82575GB_QP 0x10D6
@@ -3360,6 +3366,7 @@ struct em_host_command_info {
#define I82577_E_PHY_ID 0x01540050
#define I82578_E_PHY_ID 0x004DD040
#define I82579_E_PHY_ID 0x01540090
+#define I217_E_PHY_ID 0x015400A0
#define I82580_I_PHY_ID 0x015403A0
#define I350_I_PHY_ID 0x015403B0
#define IGP04E1000_E_PHY_ID 0x02A80391
