Now that we're no longer updating the hid0 register in the idle loop, we
can enable idle for G5.
ok?
Index: macppc/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/macppc/macppc/cpu.c,v
retrieving revision 1.76
diff -u -p -r1.76 cpu.c
--- macppc/cpu.c 6 Sep 2014 10:15:52 -0000 1.76
+++ macppc/cpu.c 6 Sep 2014 10:46:45 -0000
@@ -371,8 +371,8 @@ cpuattach(struct device *parent, struct
}
/* power savings mode */
- if (ppc_proc_is_64b == 0)
- hid0 = ppc_mfhid0();
+ hid0 = ppc_mfhid0();
+
switch (cpu) {
case PPC_CPU_MPC603:
case PPC_CPU_MPC603e:
@@ -403,14 +403,19 @@ cpuattach(struct device *parent, struct
break;
case PPC_CPU_IBM970:
case PPC_CPU_IBM970FX:
- case PPC_CPU_IBM970MP:
/* select NAP mode */
- hid0 &= ~(HID0_NAP | HID0_DOZE | HID0_SLEEP);
- hid0 |= HID0_DPM;
+ hid0 &= ~(HID0_DOZE | HID0_DEEPNAP);
+ hid0 |= HID0_NAP | HID0_DPM;
+ ppc_cpuidle = 1;
+ break;
+ case PPC_CPU_IBM970MP:
+ /* select DEEPNAP mode, which requires NAP */
+ hid0 &= ~HID0_DOZE;
+ hid0 |= HID0_DEEPNAP | HID0_NAP | HID0_DPM;
+ ppc_cpuidle = 1;
break;
}
- if (ppc_proc_is_64b == 0)
- ppc_mthid0(hid0);
+ ppc_mthid0(hid0);
/* if processor is G3 or G4, configure L2 cache */
switch (cpu) {
