On Sun, Jan 10, 2016 at 12:34:56PM +0100, Mark Kettenis wrote:
> Seems the voltage bit defenitions in sdmmcreg.h for voltages below 2V
> are not quite right. At least I can't find them in any of the MMC and
> SD card documentation I can find on the interwebs. Instead there is a
> single "low voltage bit" that indicates support for the 1.65-1.95V or
> 1.70-1.95V range depending on the document you're reading. Linux
> seems to use the slightly wider range, so that is what I did as well.
>
> This diff is necessary to support the eMMC storage on my ASUS X205TA,
> where the SDHC only supports 1.8V. Wihout this diff our code
> concludes there is no common voltage supported by both the card and
> the host controller and the card isn't enabled.
>
> ok?
You've missed the non sdhc use in armv7, diff below includes those.
No regressions spotted with the 4GB eMMC on a rev C BeagleBone Black.
The JEDEC docs refer to the range for bit 7 as 1.70-1.95, though
quite a few other documents seem to call it 1.65-1.95.
ok jsg@ with the following:
Index: dev/sdmmc/sdhc.c
===================================================================
RCS file: /cvs/src/sys/dev/sdmmc/sdhc.c,v
retrieving revision 1.39
diff -u -p -r1.39 sdhc.c
--- dev/sdmmc/sdhc.c 14 Mar 2015 03:38:49 -0000 1.39
+++ dev/sdmmc/sdhc.c 10 Jan 2016 13:32:11 -0000
@@ -198,7 +198,7 @@ sdhc_host_found(struct sdhc_softc *sc, b
* Determine SD bus voltage levels supported by the controller.
*/
if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V))
- SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
+ SET(hp->ocr, MMC_OCR_1_65V_1_95V);
if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V))
SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V))
@@ -406,7 +406,7 @@ sdhc_bus_power(sdmmc_chipset_handle_t sc
vdd = SDHC_VOLTAGE_3_3V;
else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V))
vdd = SDHC_VOLTAGE_3_0V;
- else if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V))
+ else if (ISSET(ocr, MMC_OCR_1_65V_1_95V))
vdd = SDHC_VOLTAGE_1_8V;
else {
/* Unsupported voltage level requested. */
Index: dev/sdmmc/sdmmcreg.h
===================================================================
RCS file: /cvs/src/sys/dev/sdmmc/sdmmcreg.h,v
retrieving revision 1.7
diff -u -p -r1.7 sdmmcreg.h
--- dev/sdmmc/sdmmcreg.h 8 Nov 2015 12:10:27 -0000 1.7
+++ dev/sdmmc/sdmmcreg.h 10 Jan 2016 13:32:11 -0000
@@ -67,10 +67,7 @@
#define MMC_OCR_2_2V_2_3V (1<<10)
#define MMC_OCR_2_1V_2_2V (1<<9)
#define MMC_OCR_2_0V_2_1V (1<<8)
-#define MMC_OCR_1_9V_2_0V (1<<7)
-#define MMC_OCR_1_8V_1_9V (1<<6)
-#define MMC_OCR_1_7V_1_8V (1<<5)
-#define MMC_OCR_1_6V_1_7V (1<<4)
+#define MMC_OCR_1_65V_1_95V (1<<7)
#define SD_OCR_SDHC_CAP (1<<30)
#define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
Index: arch/armv7/exynos/exesdhc.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/exynos/exesdhc.c,v
retrieving revision 1.3
diff -u -p -r1.3 exesdhc.c
--- arch/armv7/exynos/exesdhc.c 30 May 2015 02:17:36 -0000 1.3
+++ arch/armv7/exynos/exesdhc.c 10 Jan 2016 13:32:12 -0000
@@ -331,7 +331,7 @@ exesdhc_attach(struct device *parent, st
* Determine SD bus voltage levels supported by the controller.
*/
if (caps & SDHC_HOST_CTRL_CAP_VS18)
- SET(sc->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
+ SET(sc->ocr, MMC_OCR_1_65V_1_95V);
if (caps & SDHC_HOST_CTRL_CAP_VS30)
SET(sc->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
if (caps & SDHC_HOST_CTRL_CAP_VS33)
Index: arch/armv7/imx/imxesdhc.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/imx/imxesdhc.c,v
retrieving revision 1.12
diff -u -p -r1.12 imxesdhc.c
--- arch/armv7/imx/imxesdhc.c 30 May 2015 03:20:54 -0000 1.12
+++ arch/armv7/imx/imxesdhc.c 10 Jan 2016 13:32:12 -0000
@@ -281,7 +281,7 @@ imxesdhc_attach(struct device *parent, s
* Determine SD bus voltage levels supported by the controller.
*/
if (caps & SDHC_HOST_CTRL_CAP_VS18)
- SET(sc->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
+ SET(sc->ocr, MMC_OCR_1_65V_1_95V);
if (caps & SDHC_HOST_CTRL_CAP_VS30)
SET(sc->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
if (caps & SDHC_HOST_CTRL_CAP_VS33)
Index: arch/armv7/omap/ommmc.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/ommmc.c,v
retrieving revision 1.14
diff -u -p -r1.14 ommmc.c
--- arch/armv7/omap/ommmc.c 30 May 2015 02:17:36 -0000 1.14
+++ arch/armv7/omap/ommmc.c 10 Jan 2016 13:32:12 -0000
@@ -353,7 +353,7 @@ ommmc_attach(struct device *parent, stru
* Determine SD bus voltage levels supported by the controller.
*/
if (caps & MMCHS_CAPA_VS18)
- SET(sc->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
+ SET(sc->ocr, MMC_OCR_1_65V_1_95V);
if (caps & MMCHS_CAPA_VS30)
SET(sc->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
if (caps & MMCHS_CAPA_VS33)
@@ -570,7 +570,7 @@ ommmc_bus_power(sdmmc_chipset_handle_t s
vdd = MMCHS_HCTL_SDVS_V33;
else if (ISSET(ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V))
vdd = MMCHS_HCTL_SDVS_V30;
- else if (ISSET(ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V))
+ else if (ISSET(ocr, MMC_OCR_1_65V_1_95V))
vdd = MMCHS_HCTL_SDVS_V18;
else {
/* Unsupported voltage level requested. */
