On Sun, Jan 24, 2016 at 03:02:29AM +1100, Jonathan Gray wrote:
> On Sat, Jan 23, 2016 at 02:54:58PM +0100, Patrick Wildt wrote:
> > On Sun, Jan 24, 2016 at 12:33:42AM +1100, Jonathan Gray wrote:
> > > On Fri, Jan 22, 2016 at 09:36:49PM +0100, Patrick Wildt wrote:
> > > > Hi,
> > > >
> > > > the hypervisor mode, which virtualization-enabled boards might boot in,
> > > > is basically a privilege level above the usual SVC mode the kernel is
> > > > running in. It does not support the full instruction set and we, as
> > > > a "guest" OS, need to step down and run in SVC. Otherwise we crash
> > > > really early on.
> > > >
> > > > This diff makes sure the machine jumps from HYP to SVC mode, if it's
> > > > booted in HYP mode. This should enable us to run on a few more
> > > > current machines.
> > > >
> > > > If we're ever going to run virtualization on ARM, we will need to
> > > > establish a hyp mode vector table. For now this is not needed.
> > > >
> > > > This diff includes the previously sent in processor mode define diff.
> > >
> > > This seems to be based on the code in FreeBSD?
> >
> > Yes, this diff is based on the FreeBSD code.
> >
> > >
> > > I'd prefer A32_bit for consistency with the other mask bit defines
> > > but otherwise I think this should go in.
> >
> > I originally had it as A32_bit. I'm not happy that we have two
> > different naming schemes for bits in the same "register". But for
> > consistency with the mask bits, calling it A32_bit works for me.
>
> Thanks, committed with the name changed. We could change the names
> to match FreeBSD. The diff below does that and is a reminder of
> places that could be using cpsie/cpsid for v7 paths.
I like it. Looks good to me.
>
> Index: arm/arm/arm32_machdep.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/arm32_machdep.c,v
> retrieving revision 1.47
> diff -u -p -r1.47 arm32_machdep.c
> --- arm/arm/arm32_machdep.c 12 Jan 2015 16:33:31 -0000 1.47
> +++ arm/arm/arm32_machdep.c 23 Jan 2016 15:54:23 -0000
> @@ -204,7 +204,7 @@ bootsync(int howto)
> bootsyncdone = 1;
>
> /* Make sure we can still manage to do things */
> - if (__get_cpsr() & I32_bit) {
> + if (__get_cpsr() & PSR_I) {
> /*
> * If we get here then boot has been called without RB_NOSYNC
> * and interrupts were disabled. This means the boot() call
> Index: arm/arm/cpufunc_asm_sa1.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_sa1.S,v
> retrieving revision 1.5
> diff -u -p -r1.5 cpufunc_asm_sa1.S
> --- arm/arm/cpufunc_asm_sa1.S 18 Jan 2015 14:55:02 -0000 1.5
> +++ arm/arm/cpufunc_asm_sa1.S 23 Jan 2016 15:54:25 -0000
> @@ -47,7 +47,7 @@
> */
> ENTRY(sa1_setttb)
> mrs r3, cpsr
> - orr r1, r3, #(I32_bit | F32_bit)
> + orr r1, r3, #(PSR_I | PSR_F)
> msr cpsr_c, r1
>
> stmfd sp!, {r0-r3, lr}
> @@ -132,7 +132,7 @@ _C_LABEL(sa1_cache_clean_size):
>
> #define SA1_CACHE_CLEAN_BLOCK
> \
> mrs r3, cpsr ; \
> - orr r0, r3, #(I32_bit | F32_bit) ; \
> + orr r0, r3, #(PSR_I | PSR_F) ; \
> msr cpsr_c, r0
>
> #define SA1_CACHE_CLEAN_UNBLOCK
> \
> Index: arm/arm/cpufunc_asm_xscale.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_xscale.S,v
> retrieving revision 1.6
> diff -u -p -r1.6 cpufunc_asm_xscale.S
> --- arm/arm/cpufunc_asm_xscale.S 18 Jan 2015 14:55:02 -0000 1.6
> +++ arm/arm/cpufunc_asm_xscale.S 23 Jan 2016 15:54:25 -0000
> @@ -129,7 +129,7 @@ ENTRY(xscale_control)
> */
> ENTRY(xscale_setttb)
> mrs r3, cpsr
> - orr r1, r3, #(I32_bit | F32_bit)
> + orr r1, r3, #(PSR_I | PSR_F)
> msr cpsr_c, r1
>
> stmfd sp!, {r0-r3, lr}
> @@ -245,7 +245,7 @@ _C_LABEL(xscale_cache_clean_size):
>
> #define XSCALE_CACHE_CLEAN_BLOCK
> \
> mrs r3, cpsr ; \
> - orr r0, r3, #(I32_bit | F32_bit) ; \
> + orr r0, r3, #(PSR_I | PSR_F) ; \
> msr cpsr_c, r0
>
> #define XSCALE_CACHE_CLEAN_UNBLOCK
> \
> Index: arm/arm/cpuswitch.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpuswitch.S,v
> retrieving revision 1.14
> diff -u -p -r1.14 cpuswitch.S
> --- arm/arm/cpuswitch.S 12 Sep 2013 11:43:51 -0000 1.14
> +++ arm/arm/cpuswitch.S 23 Jan 2016 15:54:25 -0000
> @@ -95,12 +95,12 @@
> */
> #define IRQdisableALL \
> mrs r14, cpsr ; \
> - orr r14, r14, #(I32_bit | F32_bit) ; \
> + orr r14, r14, #(PSR_I | PSR_F) ; \
> msr cpsr_c, r14
>
> #define IRQenableALL \
> mrs r14, cpsr ; \
> - bic r14, r14, #(I32_bit | F32_bit) ; \
> + bic r14, r14, #(PSR_I | PSR_F) ; \
> msr cpsr_c, r14
>
> .text
> @@ -236,7 +236,7 @@ ENTRY(cpu_switchto)
> */
> mrs r3, cpsr
> bic r2, r3, #(PSR_MODE)
> - orr r2, r2, #(PSR_UND32_MODE | I32_bit)
> + orr r2, r2, #(PSR_UND32_MODE | PSR_I)
> msr cpsr_c, r2
>
> #ifdef notworthit
> @@ -489,7 +489,7 @@ ENTRY(proc_trampoline)
>
> /* Kill irq's */
> mrs r0, cpsr
> - orr r0, r0, #(I32_bit)
> + orr r0, r0, #(PSR_I)
> msr cpsr_c, r0
>
> PULLFRAME
> Index: arm/arm/cpuswitch7.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/cpuswitch7.S,v
> retrieving revision 1.3
> diff -u -p -r1.3 cpuswitch7.S
> --- arm/arm/cpuswitch7.S 12 Sep 2013 11:43:51 -0000 1.3
> +++ arm/arm/cpuswitch7.S 23 Jan 2016 15:54:25 -0000
> @@ -95,12 +95,12 @@
> */
> #define IRQdisableALL \
> mrs r14, cpsr ; \
> - orr r14, r14, #(I32_bit | F32_bit) ; \
> + orr r14, r14, #(PSR_I | PSR_F) ; \
> msr cpsr_c, r14
>
> #define IRQenableALL \
> mrs r14, cpsr ; \
> - bic r14, r14, #(I32_bit | F32_bit) ; \
> + bic r14, r14, #(PSR_I | PSR_F) ; \
> msr cpsr_c, r14
>
> .text
> @@ -230,7 +230,7 @@ ENTRY(cpu_switchto)
> */
> mrs r3, cpsr
> bic r2, r3, #(PSR_MODE)
> - orr r2, r2, #(PSR_UND32_MODE | I32_bit)
> + orr r2, r2, #(PSR_UND32_MODE | PSR_I)
> msr cpsr_c, r2
>
> #ifdef notworthit
> @@ -434,7 +434,7 @@ ENTRY(proc_trampoline)
>
> /* Kill irq's */
> mrs r0, cpsr
> - orr r0, r0, #(I32_bit)
> + orr r0, r0, #(PSR_I)
> msr cpsr_c, r0
>
> PULLFRAME
> Index: arm/arm/fault.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/fault.c,v
> retrieving revision 1.18
> diff -u -p -r1.18 fault.c
> --- arm/arm/fault.c 16 Nov 2014 12:30:56 -0000 1.18
> +++ arm/arm/fault.c 23 Jan 2016 15:54:25 -0000
> @@ -221,8 +221,8 @@ data_abort_handler(trapframe_t *tf)
> uvmexp.traps++;
>
> /* Re-enable interrupts if they were enabled previously */
> - if (__predict_true((tf->tf_spsr & I32_bit) == 0))
> - enable_interrupts(I32_bit);
> + if (__predict_true((tf->tf_spsr & PSR_I) == 0))
> + enable_interrupts(PSR_I);
>
> /* Get the current proc structure or proc0 if there is none */
> p = (curproc != NULL) ? curproc : &proc0;
> @@ -665,8 +665,8 @@ prefetch_abort_handler(trapframe_t *tf)
> * from user mode so we know interrupts were not disabled.
> * But we check anyway.
> */
> - if (__predict_true((tf->tf_spsr & I32_bit) == 0))
> - enable_interrupts(I32_bit);
> + if (__predict_true((tf->tf_spsr & PSR_I) == 0))
> + enable_interrupts(PSR_I);
>
> /* Get fault address */
> p = curproc;
> Index: arm/arm/fiq.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/fiq.c,v
> retrieving revision 1.6
> diff -u -p -r1.6 fiq.c
> --- arm/arm/fiq.c 16 Nov 2014 12:30:56 -0000 1.6
> +++ arm/arm/fiq.c 23 Jan 2016 15:54:25 -0000
> @@ -48,8 +48,8 @@ TAILQ_HEAD(, fiqhandler) fiqhandler_stac
> extern char fiqvector[];
> extern char fiq_nullhandler[], fiq_nullhandler_end[];
>
> -#define IRQ_BIT I32_bit
> -#define FIQ_BIT F32_bit
> +#define IRQ_BIT PSR_I
> +#define FIQ_BIT PSR_F
>
> /*
> * fiq_installhandler:
> Index: arm/arm/locore.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/locore.S,v
> retrieving revision 1.7
> diff -u -p -r1.7 locore.S
> --- arm/arm/locore.S 5 Jun 2015 05:39:54 -0000 1.7
> +++ arm/arm/locore.S 23 Jan 2016 15:54:26 -0000
> @@ -110,7 +110,7 @@ ENTRY_NP(cpu_reset)
> mrs r2, cpsr
> bic r2, r2, #(PSR_MODE)
> orr r2, r2, #(PSR_SVC32_MODE)
> - orr r2, r2, #(I32_bit | F32_bit)
> + orr r2, r2, #(PSR_I | PSR_F)
> msr cpsr_c, r2
>
> ldr r4, .Lcpu_reset_address
> Index: arm/arm/pmap.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/pmap.c,v
> retrieving revision 1.56
> diff -u -p -r1.56 pmap.c
> --- arm/arm/pmap.c 8 Sep 2015 21:28:36 -0000 1.56
> +++ arm/arm/pmap.c 23 Jan 2016 15:54:27 -0000
> @@ -2858,7 +2858,7 @@ pmap_activate(struct proc *p)
> }
>
> s = splhigh();
> - disable_interrupts(I32_bit | F32_bit);
> + disable_interrupts(PSR_I | PSR_F);
>
> /*
> * We MUST, I repeat, MUST fix up the L1 entry corresponding
> @@ -2878,7 +2878,7 @@ pmap_activate(struct proc *p)
> cpu_domains(pcb->pcb_dacr);
> cpu_setttb(pcb->pcb_pagedir);
>
> - enable_interrupts(I32_bit | F32_bit);
> + enable_interrupts(PSR_I | PSR_F);
>
> /*
> * Flag any previous userland pmap as being NOT
> @@ -2989,11 +2989,11 @@ pmap_destroy(pmap_t pm)
> * number. This will ensure pmap_remove() does not
> * pull the current vector page out from under us.
> */
> - disable_interrupts(I32_bit | F32_bit);
> + disable_interrupts(PSR_I | PSR_F);
> *pcb->pcb_pl1vec = pcb->pcb_l1vec;
> cpu_domains(pcb->pcb_dacr);
> cpu_setttb(pcb->pcb_pagedir);
> - enable_interrupts(I32_bit | F32_bit);
> + enable_interrupts(PSR_I | PSR_F);
> }
>
> /* Remove the vector page mapping */
> Index: arm/arm/pmap7.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/pmap7.c,v
> retrieving revision 1.21
> diff -u -p -r1.21 pmap7.c
> --- arm/arm/pmap7.c 8 Sep 2015 21:28:36 -0000 1.21
> +++ arm/arm/pmap7.c 23 Jan 2016 15:54:28 -0000
> @@ -2177,7 +2177,7 @@ pmap_activate(struct proc *p)
> }
>
> s = splhigh();
> - disable_interrupts(I32_bit | F32_bit);
> + disable_interrupts(PSR_I | PSR_F);
>
> /*
> * We MUST, I repeat, MUST fix up the L1 entry corresponding
> @@ -2197,7 +2197,7 @@ pmap_activate(struct proc *p)
> cpu_domains(pcb->pcb_dacr);
> cpu_setttb(pcb->pcb_pagedir);
>
> - enable_interrupts(I32_bit | F32_bit);
> + enable_interrupts(PSR_I | PSR_F);
>
> splx(s);
> }
> Index: arm/arm/process_machdep.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/process_machdep.c,v
> retrieving revision 1.4
> diff -u -p -r1.4 process_machdep.c
> --- arm/arm/process_machdep.c 20 Sep 2011 22:02:11 -0000 1.4
> +++ arm/arm/process_machdep.c 23 Jan 2016 15:54:28 -0000
> @@ -135,7 +135,7 @@ process_read_regs(struct proc *p, struct
>
> #ifdef DIAGNOSTIC
> if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE
> - && tf->tf_spsr & I32_bit)
> + && tf->tf_spsr & PSR_I)
> panic("process_read_regs: Interrupts blocked in user process");
> #endif
>
> @@ -166,7 +166,7 @@ process_write_regs(struct proc *p, struc
> tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS;
> #ifdef DIAGNOSTIC
> if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE
> - && tf->tf_spsr & I32_bit)
> + && tf->tf_spsr & PSR_I)
> panic("process_write_regs: Interrupts blocked in user process");
> #endif
>
> Index: arm/arm/sig_machdep.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/sig_machdep.c,v
> retrieving revision 1.11
> diff -u -p -r1.11 sig_machdep.c
> --- arm/arm/sig_machdep.c 26 Mar 2014 05:23:42 -0000 1.11
> +++ arm/arm/sig_machdep.c 23 Jan 2016 15:54:28 -0000
> @@ -205,7 +205,7 @@ sys_sigreturn(struct proc *p, void *v, r
> * interrupts have not been disabled.
> */
> if ((context.sc_spsr & PSR_MODE) != PSR_USR32_MODE ||
> - (context.sc_spsr & (I32_bit | F32_bit)) != 0)
> + (context.sc_spsr & (PSR_I | PSR_F)) != 0)
> return (EINVAL);
>
> /* Restore register context. */
> Index: arm/arm/syscall.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/syscall.c,v
> retrieving revision 1.17
> diff -u -p -r1.17 syscall.c
> --- arm/arm/syscall.c 11 May 2014 00:05:38 -0000 1.17
> +++ arm/arm/syscall.c 23 Jan 2016 15:54:28 -0000
> @@ -104,8 +104,8 @@ swi_handler(trapframe_t *frame)
> uvmexp.syscalls++;
>
> /* Re-enable interrupts if they were enabled previously */
> - if (__predict_true((frame->tf_spsr & I32_bit) == 0))
> - enable_interrupts(I32_bit);
> + if (__predict_true((frame->tf_spsr & PSR_I) == 0))
> + enable_interrupts(PSR_I);
>
> p->p_addr->u_pcb.pcb_tf = frame;
>
> @@ -153,7 +153,7 @@ swi_handler(trapframe_t *frame)
> frame->tf_r0 = rval[0];
> frame->tf_r1 = rval[1];
>
> - frame->tf_spsr &= ~PSR_C_bit; /* carry bit */
> + frame->tf_spsr &= ~PSR_C; /* carry bit */
> break;
>
> case ERESTART:
> @@ -170,7 +170,7 @@ swi_handler(trapframe_t *frame)
> default:
> bad:
> frame->tf_r0 = error;
> - frame->tf_spsr |= PSR_C_bit; /* carry bit */
> + frame->tf_spsr |= PSR_C; /* carry bit */
> break;
> }
>
> @@ -185,7 +185,7 @@ child_return(arg)
> struct trapframe *frame = p->p_addr->u_pcb.pcb_tf;
>
> frame->tf_r0 = 0;
> - frame->tf_spsr &= ~PSR_C_bit; /* carry bit */
> + frame->tf_spsr &= ~PSR_C; /* carry bit */
>
> mi_child_return(p);
> }
> Index: arm/arm/undefined.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/arm/undefined.c,v
> retrieving revision 1.6
> diff -u -p -r1.6 undefined.c
> --- arm/arm/undefined.c 12 Jul 2014 18:44:41 -0000 1.6
> +++ arm/arm/undefined.c 23 Jan 2016 15:54:28 -0000
> @@ -154,8 +154,8 @@ undefinedinstruction(trapframe_t *frame)
> union sigval sv;
>
> /* Enable interrupts if they were enabled before the exception. */
> - if (!(frame->tf_spsr & I32_bit))
> - enable_interrupts(I32_bit);
> + if (!(frame->tf_spsr & PSR_I))
> + enable_interrupts(PSR_I);
>
> frame->tf_pc -= INSN_SIZE;
> fault_pc = frame->tf_pc;
> Index: arm/cortex/ampintc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/cortex/ampintc.c,v
> retrieving revision 1.8
> diff -u -p -r1.8 ampintc.c
> --- arm/cortex/ampintc.c 5 Nov 2015 19:54:17 -0000 1.8
> +++ arm/cortex/ampintc.c 23 Jan 2016 15:54:28 -0000
> @@ -298,7 +298,7 @@ ampintc_attach(struct device *parent, st
> /* enable interrupts */
> bus_space_write_4(iot, d_ioh, ICD_DCR, 3);
> bus_space_write_4(iot, p_ioh, ICPICR, 1);
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
> }
>
> void
> @@ -325,7 +325,7 @@ ampintc_setipl(int new)
> int psw;
>
> /* disable here is only to keep hardware in sync with ci->ci_cpl */
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> ci->ci_cpl = new;
>
> /* low values are higher priority thus IPL_HIGH - pri */
> @@ -555,7 +555,7 @@ ampintc_intr_establish(int irqno, int le
> ih->ih_irq = irqno;
> ih->ih_name = name;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> TAILQ_INSERT_TAIL(&sc->sc_ampintc_handler[irqno].iq_list, ih, ih_list);
>
> @@ -579,7 +579,7 @@ ampintc_intr_disestablish(void *cookie)
> int psw;
> struct intrhand *ih = cookie;
> int irqno = ih->ih_irq;
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> TAILQ_REMOVE(&sc->sc_ampintc_handler[irqno].iq_list, ih, ih_list);
> if (ih->ih_name != NULL)
> evcount_detach(&ih->ih_count);
> Index: arm/include/armreg.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/armreg.h,v
> retrieving revision 1.17
> diff -u -p -r1.17 armreg.h
> --- arm/include/armreg.h 23 Jan 2016 15:38:48 -0000 1.17
> +++ arm/include/armreg.h 23 Jan 2016 15:54:29 -0000
> @@ -63,19 +63,19 @@
> */
>
> #define PSR_FLAGS 0xf0000000 /* flags */
> -#define PSR_N_bit (1U << 31) /* negative */
> -#define PSR_Z_bit (1 << 30) /* zero */
> -#define PSR_C_bit (1 << 29) /* carry */
> -#define PSR_V_bit (1 << 28) /* overflow */
> +#define PSR_N (1U << 31) /* negative */
> +#define PSR_Z (1 << 30) /* zero */
> +#define PSR_C (1 << 29) /* carry */
> +#define PSR_V (1 << 28) /* overflow */
>
> -#define PSR_Q_bit (1 << 27) /* saturation */
> +#define PSR_Q (1 << 27) /* saturation */
>
> -#define A32_bit (1 << 8) /* Asynchronous abort disable */
> -#define I32_bit (1 << 7) /* IRQ disable */
> -#define F32_bit (1 << 6) /* FIQ disable */
> +#define PSR_A (1 << 8) /* Asynchronous abort disable */
> +#define PSR_I (1 << 7) /* IRQ disable */
> +#define PSR_F (1 << 6) /* FIQ disable */
>
> -#define PSR_T_bit (1 << 5) /* Thumb state */
> -#define PSR_J_bit (1 << 24) /* Java mode */
> +#define PSR_T (1 << 5) /* Thumb state */
> +#define PSR_J (1 << 24) /* Java mode */
>
> #define PSR_MODE 0x0000001f /* mode mask */
> #define PSR_USR26_MODE 0x00000000
> Index: arm/include/atomic.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/atomic.h,v
> retrieving revision 1.12
> diff -u -p -r1.12 atomic.h
> --- arm/include/atomic.h 12 Sep 2015 16:12:50 -0000 1.12
> +++ arm/include/atomic.h 23 Jan 2016 15:54:29 -0000
> @@ -25,7 +25,7 @@ _atomic_cas_uint(volatile unsigned int *
> unsigned int cpsr;
> unsigned int rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip;
> if (rv == o)
> *uip = n;
> @@ -41,7 +41,7 @@ _atomic_cas_ulong(volatile unsigned long
> unsigned int cpsr;
> unsigned long rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip;
> if (rv == o)
> *uip = n;
> @@ -58,7 +58,7 @@ _atomic_cas_ptr(volatile void *uip, void
> void * volatile *uipp = (void * volatile *)uip;
> void *rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uipp;
> if (rv == o)
> *uipp = n;
> @@ -74,7 +74,7 @@ _atomic_swap_uint(volatile unsigned int
> unsigned int cpsr;
> unsigned int rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip;
> *uip = n;
> restore_interrupts(cpsr);
> @@ -89,7 +89,7 @@ _atomic_swap_ulong(volatile unsigned lon
> unsigned int cpsr;
> unsigned long rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip;
> *uip = n;
> restore_interrupts(cpsr);
> @@ -105,7 +105,7 @@ _atomic_swap_ptr(volatile void *uip, voi
> void * volatile *uipp = (void * volatile *)uip;
> void *rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uipp;
> *uipp = n;
> restore_interrupts(cpsr);
> @@ -120,7 +120,7 @@ _atomic_add_int_nv(volatile unsigned int
> unsigned int cpsr;
> unsigned int rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip + v;
> *uip = rv;
> restore_interrupts(cpsr);
> @@ -135,7 +135,7 @@ _atomic_add_long_nv(volatile unsigned lo
> unsigned int cpsr;
> unsigned long rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip + v;
> *uip = rv;
> restore_interrupts(cpsr);
> @@ -150,7 +150,7 @@ _atomic_sub_int_nv(volatile unsigned int
> unsigned int cpsr;
> unsigned int rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip - v;
> *uip = rv;
> restore_interrupts(cpsr);
> @@ -165,7 +165,7 @@ _atomic_sub_long_nv(volatile unsigned lo
> unsigned int cpsr;
> unsigned long rv;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> rv = *uip - v;
> *uip = rv;
> restore_interrupts(cpsr);
> @@ -179,7 +179,7 @@ atomic_setbits_int(volatile unsigned int
> {
> unsigned int cpsr;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> *uip |= v;
> restore_interrupts(cpsr);
> }
> @@ -189,7 +189,7 @@ atomic_clearbits_int(volatile unsigned i
> {
> unsigned int cpsr;
>
> - cpsr = disable_interrupts(I32_bit|F32_bit);
> + cpsr = disable_interrupts(PSR_I|PSR_F);
> *uip &= ~v;
> restore_interrupts(cpsr);
> }
> Index: arm/include/cpu.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/cpu.h,v
> retrieving revision 1.39
> diff -u -p -r1.39 cpu.h
> --- arm/include/cpu.h 11 Jul 2014 10:53:07 -0000 1.39
> +++ arm/include/cpu.h 23 Jan 2016 15:54:29 -0000
> @@ -112,20 +112,20 @@ extern int cpu_do_powersave;
> #define IRQdisable \
> stmfd sp!, {r0} ; \
> mrs r0, cpsr ; \
> - orr r0, r0, #(I32_bit) ; \
> + orr r0, r0, #(PSR_I) ; \
> msr cpsr_c, r0 ; \
> ldmfd sp!, {r0}
>
> #define IRQenable \
> stmfd sp!, {r0} ; \
> mrs r0, cpsr ; \
> - bic r0, r0, #(I32_bit) ; \
> + bic r0, r0, #(PSR_I) ; \
> msr cpsr_c, r0 ; \
> ldmfd sp!, {r0}
>
> #else
> -#define IRQdisable __set_cpsr_c(I32_bit, I32_bit);
> -#define IRQenable __set_cpsr_c(I32_bit, 0);
> +#define IRQdisable __set_cpsr_c(PSR_I, PSR_I);
> +#define IRQenable __set_cpsr_c(PSR_I, 0);
> #endif /* _LOCORE */
>
> #ifndef _LOCORE
> Index: arm/include/cpufunc.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/cpufunc.h,v
> retrieving revision 1.15
> diff -u -p -r1.15 cpufunc.h
> --- arm/include/cpufunc.h 29 Mar 2014 18:09:28 -0000 1.15
> +++ arm/include/cpufunc.h 23 Jan 2016 15:54:29 -0000
> @@ -501,14 +501,14 @@ __get_cpsr()
> }
>
> #define disable_interrupts(mask) \
> - (__set_cpsr_c((mask) & (I32_bit | F32_bit), \
> - (mask) & (I32_bit | F32_bit)))
> + (__set_cpsr_c((mask) & (PSR_I | PSR_F), \
> + (mask) & (PSR_I | PSR_F)))
>
> #define enable_interrupts(mask)
> \
> - (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
> + (__set_cpsr_c((mask) & (PSR_I | PSR_F), 0))
>
> #define restore_interrupts(old_cpsr) \
> - (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
> + (__set_cpsr_c((PSR_I | PSR_F), (old_cpsr) & (PSR_I | PSR_F)))
>
> /*
> * Functions to manipulate cpu r13
> Index: arm/include/frame.h
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/include/frame.h,v
> retrieving revision 1.6
> diff -u -p -r1.6 frame.h
> --- arm/include/frame.h 18 Jan 2015 16:26:39 -0000 1.6
> +++ arm/include/frame.h 23 Jan 2016 15:54:29 -0000
> @@ -176,8 +176,8 @@ struct frame {
> teq r0, #(PSR_USR32_MODE) ;\
> ldreq r5, .Laflt_astpending ;\
> bne 2f /* Nope, get out now */ ;\
> - bic r4, r4, #(I32_bit) ;\
> -1: orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\
> + bic r4, r4, #(PSR_I) ;\
> +1: orr r0, r4, #(PSR_I) /* Disable IRQs */ ;\
> msr cpsr_c, r0 ;\
> ldr r1, [r5] /* Pending AST? */ ;\
> teq r1, #0x00000000 ;\
> Index: arm/sa11x0/sa11x0_ost.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/sa11x0/sa11x0_ost.c,v
> retrieving revision 1.8
> diff -u -p -r1.8 sa11x0_ost.c
> --- arm/sa11x0/sa11x0_ost.c 15 May 2008 22:17:08 -0000 1.8
> +++ arm/sa11x0/sa11x0_ost.c 23 Jan 2016 15:54:29 -0000
> @@ -271,7 +271,7 @@ gettick()
> {
> int counter;
> u_int savedints;
> - savedints = disable_interrupts(I32_bit);
> + savedints = disable_interrupts(PSR_I);
>
> counter = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
> SAOST_CR);
> Index: arm/xscale/i80321_clock.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/i80321_clock.c,v
> retrieving revision 1.10
> diff -u -p -r1.10 i80321_clock.c
> --- arm/xscale/i80321_clock.c 13 Jun 2015 07:16:36 -0000 1.10
> +++ arm/xscale/i80321_clock.c 23 Jan 2016 15:54:29 -0000
> @@ -285,7 +285,7 @@ cpu_initclocks()
> int new_tps;
> int tps_diff;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> first_sec = rtctime.tv_sec;
> do {
> Index: arm/xscale/i80321_intr.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/i80321_intr.c,v
> retrieving revision 1.16
> diff -u -p -r1.16 i80321_intr.c
> --- arm/xscale/i80321_intr.c 3 Apr 2014 10:17:34 -0000 1.16
> +++ arm/xscale/i80321_intr.c 23 Jan 2016 15:54:30 -0000
> @@ -104,7 +104,7 @@ i80321intc_setipl(int new)
> {
> int psw;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> current_ipl_level = new;
> i80321intc_write_intctl(i80321intc_imask[new]);
> restore_interrupts(psw);
> @@ -177,7 +177,7 @@ i80321intc_do_pending(void)
> static int processing = 0;
> int oldirqstate, spl_save;
>
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
>
> spl_save = current_ipl_level;
>
> @@ -194,7 +194,7 @@ i80321intc_do_pending(void)
> i80321intc_setipl(ipl); \
> restore_interrupts(oldirqstate); \
> softintr_dispatch(si); \
> - oldirqstate = disable_interrupts(I32_bit); \
> + oldirqstate = disable_interrupts(PSR_I); \
> i80321intc_setipl(spl_save); \
> }
>
> @@ -253,7 +253,7 @@ _setsoftintr(int si)
> {
> int oldirqstate;
>
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
> softint_pending |= SI_TO_IRQBIT(si);
> restore_interrupts(oldirqstate);
>
> @@ -296,7 +296,7 @@ i80321intc_init(void)
> i80321intc_calc_mask();
>
> /* Enable IRQs (don't yet use FIQs). */
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
> }
>
> void *
> @@ -328,7 +328,7 @@ i80321_intr_establish(int irq, int ipl,
> /* All IOP321 interrupts are level-triggered. */
> iq->iq_ist = IST_LEVEL;
>
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
>
> TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
>
> @@ -347,7 +347,7 @@ i80321_intr_disestablish(void *cookie)
> struct intrq *iq = &i80321_handler[ih->ih_irq];
> int oldirqstate;
>
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
>
> TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
> if (ih->ih_name != NULL)
> @@ -380,14 +380,14 @@ i80321_irq_handler(void *arg)
> i80321intc_setipl(i80321_handler[irq].iq_irq);
>
> /* Enable interrupt */
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
> TAILQ_FOREACH(ih, &i80321_handler[irq].iq_list, ih_list) {
> if ((ih->ih_func)( ih->ih_arg == 0
> ? frame : ih->ih_arg))
> ih->ih_count.ec_count++;
> }
> /* Disable interrupt */
> - disable_interrupts(I32_bit);
> + disable_interrupts(PSR_I);
> hwpend &= ~(1<<irq);
> }
> uvmexp.intrs++;
> Index: arm/xscale/i80321_pci.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/i80321_pci.c,v
> retrieving revision 1.4
> diff -u -p -r1.4 i80321_pci.c
> --- arm/xscale/i80321_pci.c 4 Dec 2010 17:06:31 -0000 1.4
> +++ arm/xscale/i80321_pci.c 23 Jan 2016 15:54:30 -0000
> @@ -67,7 +67,7 @@ int i80321_pci_conf_size(void *, pcitag
> pcireg_t i80321_pci_conf_read(void *, pcitag_t, int);
> void i80321_pci_conf_write(void *, pcitag_t, int, pcireg_t);
>
> -#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
> +#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
> #define PCI_CONF_UNLOCK(s) restore_interrupts((s))
>
> void
> Index: arm/xscale/pxa2x0.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0.c,v
> retrieving revision 1.19
> diff -u -p -r1.19 pxa2x0.c
> --- arm/xscale/pxa2x0.c 18 Oct 2014 12:21:56 -0000 1.19
> +++ arm/xscale/pxa2x0.c 23 Jan 2016 15:54:30 -0000
> @@ -285,7 +285,7 @@ pxaip_measure_cpuclock(struct pxaip_soft
> int irq;
>
> ioh = sc->sc_bush_rtc;
> - irq = disable_interrupts(I32_bit|F32_bit);
> + irq = disable_interrupts(PSR_I|PSR_F);
>
> __asm volatile( "mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save));
> /* Enable clock counter */
> Index: arm/xscale/pxa2x0_apm.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0_apm.c,v
> retrieving revision 1.43
> diff -u -p -r1.43 pxa2x0_apm.c
> --- arm/xscale/pxa2x0_apm.c 20 Sep 2014 09:28:24 -0000 1.43
> +++ arm/xscale/pxa2x0_apm.c 23 Jan 2016 15:54:31 -0000
> @@ -900,7 +900,7 @@ pxa2x0_apm_sleep(struct pxa2x0_apm_softc
> goto out;
> }
>
> - save = disable_interrupts(I32_bit|F32_bit);
> + save = disable_interrupts(PSR_I|PSR_F);
>
> sd.sd_oscr0 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR0);
> sd.sd_oscr4 = bus_space_read_4(sc->sc_iot, ost_ioh, OST_OSCR4);
> @@ -1483,7 +1483,7 @@ pxa2x0_setperf(int speed)
> DPRINTF(("setperf speed %d newfreq %d, maxfreq %d\n",
> speed, newfreq, xscale_maxspeed));
>
> - s = disable_interrupts(I32_bit|F32_bit);
> + s = disable_interrupts(PSR_I|PSR_F);
>
> if (newfreq == 91) {
> if (freq > 91) {
> Index: arm/xscale/pxa2x0_apm_asm.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0_apm_asm.S,v
> retrieving revision 1.4
> diff -u -p -r1.4 pxa2x0_apm_asm.S
> --- arm/xscale/pxa2x0_apm_asm.S 2 Nov 2007 05:18:25 -0000 1.4
> +++ arm/xscale/pxa2x0_apm_asm.S 23 Jan 2016 15:54:31 -0000
> @@ -166,31 +166,31 @@ ENTRY(pxa2x0_cpu_suspend)
> str r2, [r3], #4 /* Save SVC saved CPSR. */
> str sp, [r3], #4 /* Save SVC stack pointer. */
>
> - mov r1, #(PSR_FIQ32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_FIQ32_MODE | PSR_I | PSR_F)
> msr cpsr, r1 /* Enter FIQ mode. */
> mrs r2, spsr /* Load FIQ mode saved CPSR. */
> stmia r3!, {r2, r8-r12, sp, lr} /* Save FIQ mode registers. */
>
> - mov r1, #(PSR_IRQ32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_IRQ32_MODE | PSR_I | PSR_F)
> msr cpsr, r1 /* Enter IRQ mode. */
> mrs r0, spsr /* Load IRQ mode saved CPSR. */
> stmia r3!, {r0, sp, lr} /* Save IRQ mode registers. */
>
> - mov r1, #(PSR_ABT32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_ABT32_MODE | PSR_I | PSR_F)
> msr cpsr, r1 /* Enter ABT mode. */
> mrs r0, spsr /* Load ABT mode saved CPSR. */
> stmia r3!, {r0, sp, lr} /* Save ABT mode registers. */
>
> - mov r1, #(PSR_UND32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_UND32_MODE | PSR_I | PSR_F)
> msr cpsr, r1 /* Enter UND mode. */
> mrs r0, spsr /* Load UND mode saved CPSR. */
> stmia r3!, {r0, sp, lr} /* Save UND mode registers. */
>
> - mov r1, #(PSR_SYS32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_SYS32_MODE | PSR_I | PSR_F)
> msr cpsr, r1 /* Enter SYS mode. */
> stmia r3!, {sp, lr} /* Save SYS mode registers. */
>
> - mov r1, #(PSR_SVC32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_SVC32_MODE | PSR_I | PSR_F)
> msr cpsr, r1 /* Return to SVC mode. */
>
> /* At this point all critical registers have been saved. */
> @@ -211,14 +211,14 @@ ENTRY(pxa2x0_cpu_suspend)
>
> cache_flush_loop:
> mrs r2, cpsr
> - orr r2, r2, #(I32_bit|F32_bit)
> + orr r2, r2, #(PSR_I|PSR_F)
> msr cpsr_c, r2 /* disable IRQ/FIQ */
>
> mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */
> mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */
>
> mrs r2, cpsr
> - and r2, r2, #~(I32_bit|F32_bit)
> + and r2, r2, #~(PSR_I|PSR_F)
> msr cpsr_c, r2 /* enable IRQ/FIQ */
>
> add r0, r0, #CACHELINESIZE
> @@ -329,7 +329,7 @@ pxa2x0_cpu_resume_virt:
> ldr sp, [r2], #4
>
> /* Restore FIQ mode registers. */
> - mov r1, #(PSR_FIQ32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_FIQ32_MODE | PSR_I | PSR_F)
> msr cpsr, r1
> ldr r0, [r2], #4
> msr spsr, r0
> @@ -342,7 +342,7 @@ pxa2x0_cpu_resume_virt:
> ldr lr, [r2], #4
>
> /* Restore IRQ mode registers. */
> - mov r1, #(PSR_IRQ32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_IRQ32_MODE | PSR_I | PSR_F)
> msr cpsr, r1
> ldr r0, [r2], #4
> msr spsr, r0
> @@ -350,7 +350,7 @@ pxa2x0_cpu_resume_virt:
> ldr lr, [r2], #4
>
> /* Restore ABT mode registers. */
> - mov r1, #(PSR_ABT32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_ABT32_MODE | PSR_I | PSR_F)
> msr cpsr, r1
> ldr r0, [r2], #4
> msr spsr, r0
> @@ -358,7 +358,7 @@ pxa2x0_cpu_resume_virt:
> ldr lr, [r2], #4
>
> /* Restore UND mode registers. */
> - mov r1, #(PSR_UND32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_UND32_MODE | PSR_I | PSR_F)
> msr cpsr, r1
> ldr r0, [r2], #4
> msr spsr, r0
> @@ -366,13 +366,13 @@ pxa2x0_cpu_resume_virt:
> ldr lr, [r2], #4
>
> /* Restore SYS mode registers. */
> - mov r1, #(PSR_SYS32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_SYS32_MODE | PSR_I | PSR_F)
> msr cpsr, r1
> ldr sp, [r2], #4
> ldr lr, [r2], #4
>
> /* Return to SVC mode. */
> - mov r1, #(PSR_SVC32_MODE | I32_bit | F32_bit)
> + mov r1, #(PSR_SVC32_MODE | PSR_I | PSR_F)
> msr cpsr, r1
>
> ldmia sp!, {r0-r12, pc}
> Index: arm/xscale/pxa2x0_gpio.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0_gpio.c,v
> retrieving revision 1.24
> diff -u -p -r1.24 pxa2x0_gpio.c
> --- arm/xscale/pxa2x0_gpio.c 12 Jul 2014 18:44:41 -0000 1.24
> +++ arm/xscale/pxa2x0_gpio.c 23 Jan 2016 15:54:31 -0000
> @@ -338,7 +338,7 @@ void
> pxa2x0_gpio_intr_fixup(int minipl, int maxipl)
> {
> struct pxagpio_softc *sc = pxagpio_softc;
> - int save = disable_interrupts(I32_bit);
> + int save = disable_interrupts(PSR_I);
>
> if (maxipl == IPL_NONE && minipl == IPL_HIGH) {
> /* no remaining interrupts */
> Index: arm/xscale/pxa2x0_intr.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0_intr.c,v
> retrieving revision 1.26
> diff -u -p -r1.26 pxa2x0_intr.c
> --- arm/xscale/pxa2x0_intr.c 12 Jul 2014 18:44:41 -0000 1.26
> +++ arm/xscale/pxa2x0_intr.c 23 Jan 2016 15:54:32 -0000
> @@ -158,7 +158,7 @@ pxaintc_attach(struct device *parent, st
> pxa2x0_init_interrupt_masks();
>
> _splraise(IPL_HIGH);
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
> }
>
> /*
> @@ -219,7 +219,7 @@ pxa2x0_irq_handler(void *arg)
> pxa2x0_setipl(extirq_level[irqno]);
>
> /* Enable interrupt */
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
>
> #ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
> (* handler[irqno].func)(
> @@ -235,7 +235,7 @@ pxa2x0_irq_handler(void *arg)
> #endif
>
> /* Disable interrupt */
> - disable_interrupts(I32_bit);
> + disable_interrupts(PSR_I);
>
> irqbits &= ~(1<<irqno);
> }
> @@ -254,7 +254,7 @@ pxa2x0_stray_interrupt(void *cookie)
> printf("stray interrupt %d\n", irqno);
>
> if (PXA2X0_IRQ_MIN <= irqno && irqno < ICU_LEN){
> - int save = disable_interrupts(I32_bit);
> + int save = disable_interrupts(PSR_I);
> write_icu(SAIPIC_MR,
> read_icu(SAIPIC_MR) & ~(1U<<irqno));
> restore_interrupts(save);
> @@ -289,7 +289,7 @@ pxa2x0_update_intr_masks(int irqno, int
> int level;
> #endif
> struct intrhand *ih;
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> /* First figure out which levels each IRQ uses. */
> for (irq = 0; irq < ICU_LEN; irq++) {
> @@ -339,7 +339,7 @@ pxa2x0_update_intr_masks(int irqno, int
> int level; /* debug */
> int mask = 1U<<irqno;
> int i;
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> for(i = 0; i < irqlevel; ++i)
> pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
> @@ -456,7 +456,7 @@ pxa2x0_do_pending(void)
>
> spl_save = current_spl_level;
>
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
>
> #if 1
> #define DO_SOFTINT(si,ipl)
> \
> @@ -467,7 +467,7 @@ pxa2x0_do_pending(void)
> pxa2x0_setipl(ipl); \
> restore_interrupts(oldirqstate); \
> softintr_dispatch(si); \
> - oldirqstate = disable_interrupts(I32_bit); \
> + oldirqstate = disable_interrupts(PSR_I); \
> pxa2x0_setipl(spl_save); \
> }
>
> @@ -484,7 +484,7 @@ pxa2x0_do_pending(void)
> pxa2x0_setipl(ipl);
> restore_interrupts(oldirqstate);
> softintr_dispatch(si);
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
> pxa2x0_setipl(spl_save);
> }
> #endif
> @@ -541,7 +541,7 @@ pxa2x0_intr_establish(int irqno, int lev
> if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN)
> panic("intr_establish: bogus irq number %d", irqno);
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
> /* no point in sleeping unless someone can free memory. */
> @@ -587,7 +587,7 @@ pxa2x0_intr_disestablish(void *cookie)
> struct intrhand *ih = cookie;
> int irqno = ih->ih_irq;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> TAILQ_REMOVE(&handler[irqno].list, ih, ih_list);
>
> free(ih, M_DEVBUF, 0);
> @@ -605,7 +605,7 @@ pxa2x0_intr_disestablish(void *cookie)
> if (irqno < PXA2X0_IRQ_MIN || irqno >= ICU_LEN)
> panic("intr_disestablish: bogus irq number %d", irqno);
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> ih = &handler[irqno];
> if (ih->name != NULL)
> @@ -648,7 +648,7 @@ pxa2x0_splx(int new)
> {
> int psw;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> pxa2x0_setipl(new);
> restore_interrupts(psw);
>
> @@ -665,7 +665,7 @@ pxa2x0_splraise(int ipl)
>
> old = current_spl_level;
> if( ipl > current_spl_level ){
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> pxa2x0_setipl(ipl);
> restore_interrupts(psw);
> }
> @@ -677,7 +677,7 @@ int
> pxa2x0_spllower(int ipl)
> {
> int old = current_spl_level;
> - int psw = disable_interrupts(I32_bit);
> + int psw = disable_interrupts(PSR_I);
> pxa2x0_splx(ipl);
> restore_interrupts(psw);
> return(old);
> @@ -723,7 +723,7 @@ pxa2x0_splassert_check(int wantipl, cons
> * If the splassert_ctl is set to not panic, raise the ipl
> * in a feeble attempt to reduce damage.
> */
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> pxa2x0_setipl(wantipl);
> restore_interrupts(psw);
> }
> Index: arm/xscale/pxa2x0_lcd.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0_lcd.c,v
> retrieving revision 1.26
> diff -u -p -r1.26 pxa2x0_lcd.c
> --- arm/xscale/pxa2x0_lcd.c 12 Jul 2014 18:44:41 -0000 1.26
> +++ arm/xscale/pxa2x0_lcd.c 23 Jan 2016 15:54:32 -0000
> @@ -292,7 +292,7 @@ pxa2x0_lcd_start_dma(bus_space_tag_t iot
> uint32_t tmp;
> int val, save;
>
> - save = disable_interrupts(I32_bit);
> + save = disable_interrupts(PSR_I);
>
> switch (scr->depth) {
> case 1: val = 0; break;
> Index: armv7/armv7/armv7_start.S
> ===================================================================
> RCS file: /cvs/src/sys/arch/armv7/armv7/armv7_start.S,v
> retrieving revision 1.4
> diff -u -p -r1.4 armv7_start.S
> --- armv7/armv7/armv7_start.S 23 Jan 2016 15:38:48 -0000 1.4
> +++ armv7/armv7/armv7_start.S 23 Jan 2016 15:54:33 -0000
> @@ -102,7 +102,7 @@ _C_LABEL(bootstrap_start):
> mrs r0, cpsr
> bic r0, r0, #(PSR_MODE)
> orr r0, r0, #(PSR_SVC32_MODE)
> - orr r0, r0, #(I32_bit | F32_bit | A32_bit)
> + orr r0, r0, #(PSR_I | PSR_F | PSR_A)
> msr spsr_fsxc, r0
> adr lr, 1f
> ELR
> Index: armv7/armv7/intr.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/armv7/armv7/intr.c,v
> retrieving revision 1.3
> diff -u -p -r1.3 intr.c
> --- armv7/armv7/intr.c 13 Jun 2015 07:16:37 -0000 1.3
> +++ armv7/armv7/intr.c 23 Jan 2016 15:54:33 -0000
> @@ -151,7 +151,7 @@ arm_setsoftintr(int si)
> int oldirqstate;
>
> /* XXX atomic? */
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
> ci->ci_ipending |= SI_TO_IRQBIT(si);
>
> restore_interrupts(oldirqstate);
> @@ -168,7 +168,7 @@ arm_do_pending_intr(int pcpl)
> static int processing = 0;
> int oldirqstate;
>
> - oldirqstate = disable_interrupts(I32_bit);
> + oldirqstate = disable_interrupts(PSR_I);
>
> if (processing == 1) {
> /* Don't use splx... we are here already! */
> @@ -184,7 +184,7 @@ arm_do_pending_intr(int pcpl)
> arm_intr_func.setipl(ipl); \
> restore_interrupts(oldirqstate); \
> softintr_dispatch(si); \
> - oldirqstate = disable_interrupts(I32_bit); \
> + oldirqstate = disable_interrupts(PSR_I); \
> }
>
> do {
> Index: armv7/omap/intc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/armv7/omap/intc.c,v
> retrieving revision 1.3
> diff -u -p -r1.3 intc.c
> --- armv7/omap/intc.c 12 Jul 2014 18:44:41 -0000 1.3
> +++ armv7/omap/intc.c 23 Jan 2016 15:54:34 -0000
> @@ -170,7 +170,7 @@ intc_attach(struct device *parent, struc
> intc_irq_handler);
>
> intc_setipl(IPL_HIGH); /* XXX ??? */
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
> }
>
> void
> @@ -269,7 +269,7 @@ intc_setipl(int new)
> if (intc_attached == 0)
> return;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> #if 0
> {
> volatile static int recursed = 0;
> @@ -342,7 +342,7 @@ intc_intr_establish(int irqno, int level
> if (irqno < 0 || irqno >= INTC_NUM_IRQ)
> panic("intc_intr_establish: bogus irqnumber %d: %s",
> irqno, name);
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> /* no point in sleeping unless someone can free memory. */
> ih = (struct intrhand *)malloc (sizeof *ih, M_DEVBUF,
> @@ -376,7 +376,7 @@ intc_intr_disestablish(void *cookie)
> int psw;
> struct intrhand *ih = cookie;
> int irqno = ih->ih_irq;
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> TAILQ_REMOVE(&intc_handler[irqno].iq_list, ih, ih_list);
> if (ih->ih_name != NULL)
> evcount_detach(&ih->ih_count);
> Index: armv7/omap/omgpio.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/armv7/omap/omgpio.c,v
> retrieving revision 1.5
> diff -u -p -r1.5 omgpio.c
> --- armv7/omap/omgpio.c 14 Jul 2014 08:55:07 -0000 1.5
> +++ armv7/omap/omgpio.c 23 Jan 2016 15:54:36 -0000
> @@ -621,7 +621,7 @@ omgpio_intr_establish(struct omgpio_soft
> gpio, sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)]->ih_name,
> name);
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> /* no point in sleeping unless someone can free memory. */
> ih = (struct intrhand *)malloc( sizeof *ih, M_DEVBUF,
> @@ -656,7 +656,7 @@ omgpio_intr_disestablish(struct omgpio_s
> struct intrhand *ih = cookie;
> struct omgpio_softc *sc =
> omgpio_cd.cd_devs[GPIO_PIN_TO_INST(ih->ih_gpio)];
> int gpio = ih->ih_gpio;
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> ih = sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)];
> sc->sc_handlers[GPIO_PIN_TO_OFFSET(gpio)] = NULL;
> Index: armv7/sunxi/a1xintc.c
> ===================================================================
> RCS file: /cvs/src/sys/arch/armv7/sunxi/a1xintc.c,v
> retrieving revision 1.6
> diff -u -p -r1.6 a1xintc.c
> --- armv7/sunxi/a1xintc.c 20 May 2015 03:49:23 -0000 1.6
> +++ armv7/sunxi/a1xintc.c 23 Jan 2016 15:54:36 -0000
> @@ -194,7 +194,7 @@ a1xintc_attach(struct device *parent, st
> a1xintc_intr_establish, a1xintc_intr_disestablish,
> a1xintc_intr_string,
> a1xintc_irq_handler);
> a1xintc_setipl(IPL_HIGH); /* XXX ??? */
> - enable_interrupts(I32_bit);
> + enable_interrupts(PSR_I);
> printf("\n");
> }
>
> @@ -297,7 +297,7 @@ a1xintc_setipl(int new)
> return;
> }
> #endif
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
> ci->ci_cpl = new;
> for (i = 0; i < NBANKS; i++)
> bus_space_write_4(a1xintc_iot, a1xintc_ioh,
> @@ -365,7 +365,7 @@ a1xintc_intr_establish(int irq, int lvl,
> DPRINTF(("intr_establish: irq %d level %d [%s]\n", irq, lvl,
> name != NULL ? name : "NULL"));
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> /* no point in sleeping unless someone can free memory. */
> ih = (struct intrhand *)malloc (sizeof *ih, M_DEVBUF,
> @@ -403,7 +403,7 @@ a1xintc_intr_disestablish(void *cookie)
> int psw;
> uint32_t er;
>
> - psw = disable_interrupts(I32_bit);
> + psw = disable_interrupts(PSR_I);
>
> TAILQ_REMOVE(&a1xintc_handler[irq].iq_list, ih, ih_list);
>
>
