On Wed, Mar 09, 2016 at 09:14:06AM +0100, Patrick Wildt wrote:
> On Wed, Mar 09, 2016 at 01:28:55PM +1100, Jonathan Gray wrote:
> > On Tue, Mar 08, 2016 at 10:59:42PM +0100, Patrick Wildt wrote:
> > > Hi,
> > >
> > > I'd like to get some opinions on this. ARM8 has probably never ever
> > > been used with OpenBSD, and I doubt it will ever be. I think it also
> > > makes sense to remove more, like ARM9, ARM9E, ARM10, ARM11. All the
> > > cruft that is not used, apart from armish, armv7 and zaurus.
> > >
> > > In the end it will probably only make sense to support >=ARMv6, which
> > > does not include armish and zaurus. Not sure how long those will still
> > > be around though.
> > >
> > > This diff removes ARM8 first, I can follow up with more diffs quickly.
> > >
> > > Thoughts?
> > >
> > > Patrick
> >
> > StrongARM is ARM8 but has it's own CPU_SA1100 that would have been used
> > by OpenBSD/cats.
> >
> > But cats was dropped a long time ago (4.0). It seems it may not be
> > possible to do eabi without requiring at least armv4t.
> >
> > armish is CPU_XSCALE_80321
> > zaurus is CPU_XSCALE_PXA2X0
> >
> > so we'd just keep the xscale variants and CPU_ARMv7?
> >
> > CPU_XSCALE_80200
> > CPU_XSCALE_80321
> > CPU_XSCALE_PXA2X0
> > CPU_XSCALE_IXP425
> > CPU_ARMv7
>
> We can also safely drop 80200 and IXP425. That allows us to lose some
> more unused code without harming armish or zaurus.
>
> >
> > currently the gcc configuration in base has
> > #define SUBTARGET_CPU_DEFAULT TARGET_CPU_strongarm
> > that could also change to something like TARGET_CPU_arm10tdmi
> > if the new baseline becomes armv5 instead of armv4.
> >
>
> Yeah, that's at least a tiny jump.
>
> > >
> > > diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
> > > index bc96e79..12709b1 100644
> > > --- sys/arch/arm/arm/cpu.c
> > > +++ sys/arch/arm/arm/cpu.c
> > > @@ -80,36 +80,10 @@ cpu_attach(struct device *dv)
> > > curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK;
> > >
> > > identify_arm_cpu(dv, curcpu());
> > > -
> > > -#ifdef CPU_ARM8
> > > - if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
> > > - int clock = arm8_clock_config(0, 0);
> > > - char *fclk;
> > > - aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock);
> > > - aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : "");
> > > - aprint_normal("%s", (clock & 2) ? " sync" : "");
> > > - switch ((clock >> 2) & 3) {
> > > - case 0:
> > > - fclk = "bus clock";
> > > - break;
> > > - case 1:
> > > - fclk = "ref clock";
> > > - break;
> > > - case 3:
> > > - fclk = "pll";
> > > - break;
> > > - default:
> > > - fclk = "illegal";
> > > - break;
> > > - }
> > > - aprint_normal(" fclk source=%s\n", fclk);
> > > - }
> > > -#endif
> > > }
> > >
> > > enum cpu_class {
> > > CPU_CLASS_NONE,
> > > - CPU_CLASS_ARM8,
> > > CPU_CLASS_ARM9TDMI,
> > > CPU_CLASS_ARM9ES,
> > > CPU_CLASS_ARM9EJS,
> > > @@ -219,9 +193,6 @@ struct cpuidtab {
> > > };
> > >
> > > const struct cpuidtab cpuids[] = {
> > > - { CPU_ID_ARM810, CPU_CLASS_ARM8, "ARM810",
> > > - generic_steppings },
> > > -
> > > { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T",
> > > generic_steppings },
> > > { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T",
> > > @@ -358,7 +329,6 @@ struct cpu_classtab {
> > >
> > > const struct cpu_classtab cpu_classes[] = {
> > > { "unknown", NULL }, /* CPU_CLASS_NONE */
> > > - { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */
> > > { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */
> > > { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
> > > { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
> > > @@ -429,12 +399,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info
> > > *ci)
> > > printf("%s:", dv->dv_xname);
> > >
> > > switch (cpu_class) {
> > > - case CPU_CLASS_ARM8:
> > > - if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
> > > - printf(" IDC disabled");
> > > - else
> > > - printf(" IDC enabled");
> > > - break;
> > > case CPU_CLASS_ARM9TDMI:
> > > case CPU_CLASS_ARM9ES:
> > > case CPU_CLASS_ARM9EJS:
> > > @@ -490,9 +454,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info
> > > *ci)
> > > skip_pcache:
> > >
> > > switch (cpu_class) {
> > > -#ifdef CPU_ARM8
> > > - case CPU_CLASS_ARM8:
> > > -#endif
> > > #ifdef CPU_ARM9
> > > case CPU_CLASS_ARM9TDMI:
> > > #endif
> > > diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
> > > index f549e61..4c2c6d8 100644
> > > --- sys/arch/arm/arm/cpufunc.c
> > > +++ sys/arch/arm/arm/cpufunc.c
> > > @@ -97,63 +97,6 @@ int arm_dcache_align_mask;
> > > /* 1 == use cpu_sleep(), 0 == don't */
> > > int cpu_do_powersave;
> > >
> > > -#ifdef CPU_ARM8
> > > -struct cpu_functions arm8_cpufuncs = {
> > > - /* CPU functions */
> > > -
> > > - cpufunc_id, /* id */
> > > - cpufunc_nullop, /* cpwait */
> > > -
> > > - /* MMU functions */
> > > -
> > > - cpufunc_control, /* control */
> > > - cpufunc_domains, /* domain */
> > > - arm8_setttb, /* setttb */
> > > - cpufunc_dfsr, /* dfsr */
> > > - cpufunc_dfar, /* dfar */
> > > - cpufunc_ifsr, /* ifsr */
> > > - cpufunc_ifar, /* ifar */
> > > -
> > > - /* TLB functions */
> > > -
> > > - arm8_tlb_flushID, /* tlb_flushID */
> > > - arm8_tlb_flushID_SE, /* tlb_flushID_SE */
> > > - arm8_tlb_flushID, /* tlb_flushI */
> > > - arm8_tlb_flushID_SE, /* tlb_flushI_SE */
> > > - arm8_tlb_flushID, /* tlb_flushD */
> > > - arm8_tlb_flushID_SE, /* tlb_flushD_SE */
> > > -
> > > - /* Cache operations */
> > > -
> > > - cpufunc_nullop, /* icache_sync_all */
> > > - (void *)cpufunc_nullop, /* icache_sync_range */
> > > -
> > > - arm8_cache_purgeID, /* dcache_wbinv_all */
> > > - (void *)arm8_cache_purgeID, /* dcache_wbinv_range */
> > > -/*XXX*/ (void *)arm8_cache_purgeID, /* dcache_inv_range */
> > > - (void *)arm8_cache_cleanID, /* dcache_wb_range */
> > > -
> > > - arm8_cache_purgeID, /* idcache_wbinv_all */
> > > - (void *)arm8_cache_purgeID, /* idcache_wbinv_range */
> > > -
> > > - cpufunc_nullop, /* sdcache_wbinv_all */
> > > - (void *)cpufunc_nullop, /* sdcache_wbinv_range */
> > > - (void *)cpufunc_nullop, /* sdcache_inv_range */
> > > - (void *)cpufunc_nullop, /* sdcache_wb_range */
> > > -
> > > - /* Other functions */
> > > -
> > > - cpufunc_nullop, /* flush_prefetchbuf */
> > > - cpufunc_nullop, /* drain_writebuf */
> > > -
> > > - (void *)cpufunc_nullop, /* sleep */
> > > -
> > > - /* Soft functions */
> > > - arm8_context_switch, /* context_switch */
> > > - arm8_setup /* cpu setup */
> > > -};
> > > -#endif /* CPU_ARM8 */
> > > -
> > > #ifdef CPU_ARM9
> > > struct cpu_functions arm9_cpufuncs = {
> > > /* CPU functions */
> > > @@ -624,7 +567,7 @@ struct cpu_functions cpufuncs;
> > > u_int cputype;
> > > u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
> > >
> > > -#if defined(CPU_ARM8) || defined(CPU_ARM9) || \
> > > +#if defined(CPU_ARM9) || \
> > > defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
> > > defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
> > > defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
> > > @@ -704,7 +647,7 @@ get_cachetype_cp15()
> > > out:
> > > arm_dcache_align_mask = arm_dcache_align - 1;
> > > }
> > > -#endif /* ARM7TDMI || ARM8 || ARM9 || XSCALE */
> > > +#endif /* ARM7TDMI || ARM9 || XSCALE */
> > >
> > > #if defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
> > > /* Cache information for CPUs without cache type registers. */
> > > @@ -922,16 +865,6 @@ set_cpufuncs()
> > > * CPU type where we want to use it by default, then we set it.
> > > */
> > >
> > > -#ifdef CPU_ARM8
> > > - if ((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD &&
> > > - (cputype & 0x0000f000) == 0x00008000) {
> > > - cpufuncs = arm8_cpufuncs;
> > > - cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
> > > - get_cachetype_cp15();
> > > - pmap_pte_init_arm8();
> > > - return 0;
> > > - }
> > > -#endif /* CPU_ARM8 */
> > > #ifdef CPU_ARM9
> > > if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
> > > (cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
> > > @@ -1197,41 +1130,6 @@ set_cpufuncs()
> > > * CPU Setup code
> > > */
> > >
> > > -#ifdef CPU_ARM8
> > > -void
> > > -arm8_setup()
> > > -{
> > > - int integer;
> > > - int cpuctrl, cpuctrlmask;
> > > - int clocktest;
> > > - int setclock = 0;
> > > -
> > > - cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
> > > - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
> > > - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
> > > - | CPU_CONTROL_AFLT_ENABLE;
> > > - cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
> > > - | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
> > > - | CPU_CONTROL_IDC_ENABLE | CPU_CONTROL_WBUF_ENABLE
> > > - | CPU_CONTROL_BPRD_ENABLE | CPU_CONTROL_ROM_ENABLE
> > > - | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE;
> > > -
> > > - /* Get clock configuration */
> > > - clocktest = arm8_clock_config(0, 0) & 0x0f;
> > > -
> > > - /* Clear out the cache */
> > > - cpu_idcache_wbinv_all();
> > > -
> > > - /* Set the control register */
> > > - curcpu()->ci_ctrl = cpuctrl;
> > > - cpu_control(0xffffffff, cpuctrl);
> > > -
> > > - /* Set the clock/test register */
> > > - if (setclock)
> > > - arm8_clock_config(0x7f, clocktest);
> > > -}
> > > -#endif /* CPU_ARM8 */
> > > -
> > > #ifdef CPU_ARM9
> > > void
> > > arm9_setup()
> > > diff --git sys/arch/arm/arm/pmap.c sys/arch/arm/arm/pmap.c
> > > index dda550f..627f4d5 100644
> > > --- sys/arch/arm/arm/pmap.c
> > > +++ sys/arch/arm/arm/pmap.c
> > > @@ -4439,23 +4439,6 @@ pmap_pte_init_generic(void)
> > > pmap_zero_page_func = pmap_zero_page_generic;
> > > }
> > >
> > > -#if defined(CPU_ARM8)
> > > -void
> > > -pmap_pte_init_arm8(void)
> > > -{
> > > -
> > > - /*
> > > - * ARM8 is compatible with generic, but we need to use
> > > - * the page tables uncached.
> > > - */
> > > - pmap_pte_init_generic();
> > > -
> > > - pte_l1_s_cache_mode_pt = 0;
> > > - pte_l2_l_cache_mode_pt = 0;
> > > - pte_l2_s_cache_mode_pt = 0;
> > > -}
> > > -#endif /* CPU_ARM8 */
> > > -
> > > #if defined(CPU_ARM9)
> > > void
> > > pmap_pte_init_arm9(void)
> > > diff --git sys/arch/arm/conf/files.arm sys/arch/arm/conf/files.arm
> > > index 0365078..857e7e6 100644
> > > --- sys/arch/arm/conf/files.arm
> > > +++ sys/arch/arm/conf/files.arm
> > > @@ -39,7 +39,6 @@ file arch/arm/arm/bcopyinout.S
> > > file arch/arm/arm/copystr.S
> > > file arch/arm/arm/cpufunc.c
> > > file arch/arm/arm/cpufunc_asm.S
> > > -file arch/arm/arm/cpufunc_asm_arm8.S cpu_arm8
> > > file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9
> > > file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
> > > file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_arm9e |
> > > diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
> > > index 68fb253..f2a5854 100644
> > > --- sys/arch/arm/include/armreg.h
> > > +++ sys/arch/arm/include/armreg.h
> > > @@ -176,7 +176,6 @@
> > > #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
> > >
> > > /* Post-ARM7 CPUs */
> > > -#define CPU_ID_ARM810 0x41018100
> > > #define CPU_ID_ARM920T 0x41129200
> > > #define CPU_ID_ARM922T 0x41029220
> > > #define CPU_ID_ARM926EJS 0x41069260
> > > diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
> > > index 4a64e12..6ed95ee 100644
> > > --- sys/arch/arm/include/cpuconf.h
> > > +++ sys/arch/arm/include/cpuconf.h
> > > @@ -48,7 +48,7 @@
> > > /*
> > > * Determine which ARM architecture versions are configured.
> > > */
> > > -#if (defined(CPU_ARM8) || defined(CPU_ARM9) || \
> > > +#if (defined(CPU_ARM9) || \
> > > defined(CPU_SA1100) || defined(CPU_SA1110) || \
> > > defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
> > > #define ARM_ARCH_4 1
> > > @@ -91,7 +91,7 @@
> > > * protection is not used, TEX/AP is used
> > > instead.
> > > */
> > >
> > > -#if (defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||
> > > \
> > > +#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \
> > > defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) )
> > > #define ARM_MMU_GENERIC 1
> > > #else
> > > diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
> > > index 9de47c4..416248a 100644
> > > --- sys/arch/arm/include/cpufunc.h
> > > +++ sys/arch/arm/include/cpufunc.h
> > > @@ -213,31 +213,6 @@ u_int cpufunc_dfar (void);
> > > u_int cpufunc_ifsr (void);
> > > u_int cpufunc_ifar (void);
> > >
> > > -#ifdef CPU_ARM8
> > > -void arm8_setttb (u_int ttb);
> > > -void arm8_tlb_flushID (void);
> > > -void arm8_tlb_flushID_SE (u_int va);
> > > -void arm8_cache_flushID (void);
> > > -void arm8_cache_flushID_E (u_int entry);
> > > -void arm8_cache_cleanID (void);
> > > -void arm8_cache_cleanID_E (u_int entry);
> > > -void arm8_cache_purgeID (void);
> > > -void arm8_cache_purgeID_E (u_int entry);
> > > -
> > > -void arm8_cache_syncI (void);
> > > -void arm8_cache_cleanID_rng (vaddr_t start, vsize_t end);
> > > -void arm8_cache_cleanD_rng (vaddr_t start, vsize_t end);
> > > -void arm8_cache_purgeID_rng (vaddr_t start, vsize_t end);
> > > -void arm8_cache_purgeD_rng (vaddr_t start, vsize_t end);
> > > -void arm8_cache_syncI_rng (vaddr_t start, vsize_t end);
> > > -
> > > -void arm8_context_switch (u_int);
> > > -
> > > -void arm8_setup (void);
> > > -
> > > -u_int arm8_clock_config (u_int, u_int);
> > > -#endif
> > > -
> > > #if defined(CPU_SA1100) || defined(CPU_SA1110)
> > > void sa11x0_drain_readbuf (void);
> > >
> > > diff --git sys/arch/arm/include/pmap.h sys/arch/arm/include/pmap.h
> > > index c409ad3..3851abb 100644
> > > --- sys/arch/arm/include/pmap.h
> > > +++ sys/arch/arm/include/pmap.h
> > > @@ -371,9 +371,6 @@ void pmap_copy_page_generic(struct vm_page *, struct
> > > vm_page *);
> > > void pmap_zero_page_generic(struct vm_page *);
> > >
> > > void pmap_pte_init_generic(void);
> > > -#if defined(CPU_ARM8)
> > > -void pmap_pte_init_arm8(void);
> > > -#endif
> > > #if defined(CPU_ARM9)
> > > void pmap_pte_init_arm9(void);
> > > #endif /* CPU_ARM9 */
> > >
> >
Ping. Additionally, here's the following tedu for arm9.
Patrick
diff --git sys/arch/arm/arm/cpu.c sys/arch/arm/arm/cpu.c
index 12709b1..f585442 100644
--- sys/arch/arm/arm/cpu.c
+++ sys/arch/arm/arm/cpu.c
@@ -84,7 +84,6 @@ cpu_attach(struct device *dv)
enum cpu_class {
CPU_CLASS_NONE,
- CPU_CLASS_ARM9TDMI,
CPU_CLASS_ARM9ES,
CPU_CLASS_ARM9EJS,
CPU_CLASS_ARM10E,
@@ -193,22 +192,14 @@ struct cpuidtab {
};
const struct cpuidtab cpuids[] = {
- { CPU_ID_ARM920T, CPU_CLASS_ARM9TDMI, "ARM920T",
- generic_steppings },
- { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T",
- generic_steppings },
{ CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S",
generic_steppings },
- { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T",
- generic_steppings },
{ CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S",
generic_steppings },
{ CPU_ID_ARM966ES, CPU_CLASS_ARM9ES, "ARM966E-S",
generic_steppings },
{ CPU_ID_ARM966ESR1, CPU_CLASS_ARM9ES, "ARM966E-S",
generic_steppings },
- { CPU_ID_TI925T, CPU_CLASS_ARM9TDMI, "TI ARM925T",
- generic_steppings },
{ CPU_ID_ARM1020E, CPU_CLASS_ARM10E, "ARM1020E",
generic_steppings },
@@ -329,7 +320,6 @@ struct cpu_classtab {
const struct cpu_classtab cpu_classes[] = {
{ "unknown", NULL }, /* CPU_CLASS_NONE */
- { "ARM9TDMI", NULL }, /* CPU_CLASS_ARM9TDMI */
{ "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */
{ "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */
{ "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */
@@ -399,7 +389,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
printf("%s:", dv->dv_xname);
switch (cpu_class) {
- case CPU_CLASS_ARM9TDMI:
case CPU_CLASS_ARM9ES:
case CPU_CLASS_ARM9EJS:
case CPU_CLASS_ARM10E:
@@ -454,9 +443,6 @@ identify_arm_cpu(struct device *dv, struct cpu_info *ci)
skip_pcache:
switch (cpu_class) {
-#ifdef CPU_ARM9
- case CPU_CLASS_ARM9TDMI:
-#endif
#ifdef CPU_ARM9E
case CPU_CLASS_ARM9ES:
case CPU_CLASS_ARM9EJS:
diff --git sys/arch/arm/arm/cpufunc.c sys/arch/arm/arm/cpufunc.c
index 4c2c6d8..b7663d6 100644
--- sys/arch/arm/arm/cpufunc.c
+++ sys/arch/arm/arm/cpufunc.c
@@ -97,64 +97,6 @@ int arm_dcache_align_mask;
/* 1 == use cpu_sleep(), 0 == don't */
int cpu_do_powersave;
-#ifdef CPU_ARM9
-struct cpu_functions arm9_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- cpufunc_nullop, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* Domain */
- arm9_setttb, /* Setttb */
- cpufunc_dfsr, /* dfsr */
- cpufunc_dfar, /* dfar */
- cpufunc_ifsr, /* ifsr */
- cpufunc_ifar, /* ifar */
-
- /* TLB functions */
-
- armv4_tlb_flushID, /* tlb_flushID */
- arm9_tlb_flushID_SE, /* tlb_flushID_SE */
- armv4_tlb_flushI, /* tlb_flushI */
- (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
- armv4_tlb_flushD, /* tlb_flushD */
- armv4_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
-
- arm9_icache_sync_all, /* icache_sync_all */
- arm9_icache_sync_range, /* icache_sync_range */
-
- /* ...cache in write-though mode... */
- arm9_dcache_wbinv_all, /* dcache_wbinv_all */
- arm9_dcache_wbinv_range, /* dcache_wbinv_range */
- arm9_dcache_wbinv_range, /* dcache_inv_range */
- arm9_dcache_wb_range, /* dcache_wb_range */
-
- arm9_idcache_wbinv_all, /* idcache_wbinv_all */
- arm9_idcache_wbinv_range, /* idcache_wbinv_range */
-
- cpufunc_nullop, /* sdcache_wbinv_all */
- (void *)cpufunc_nullop, /* sdcache_wbinv_range */
- (void *)cpufunc_nullop, /* sdcache_inv_range */
- (void *)cpufunc_nullop, /* sdcache_wb_range */
-
- /* Other functions */
-
- cpufunc_nullop, /* flush_prefetchbuf */
- armv4_drain_writebuf, /* drain_writebuf */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
- arm9_context_switch, /* context_switch */
- arm9_setup /* cpu setup */
-};
-#endif /* CPU_ARM9 */
-
#if defined(CPU_ARM9E) || defined(CPU_ARM10)
struct cpu_functions armv5_ec_cpufuncs = {
/* CPU functions */
@@ -567,8 +509,7 @@ struct cpu_functions cpufuncs;
u_int cputype;
u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
-#if defined(CPU_ARM9) || \
- defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
+#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_ARM11) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
static void get_cachetype_cp15 (void);
@@ -865,23 +806,6 @@ set_cpufuncs()
* CPU type where we want to use it by default, then we set it.
*/
-#ifdef CPU_ARM9
- if (((cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD ||
- (cputype & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_TI) &&
- (cputype & 0x0000f000) == 0x00009000) {
- cpufuncs = arm9_cpufuncs;
- cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
- get_cachetype_cp15();
- arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
- arm9_dcache_sets_max =
- (1U << (arm_dcache_l2_linesize + arm_dcache_l2_nsets)) -
- arm9_dcache_sets_inc;
- arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
- arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
- pmap_pte_init_arm9();
- return 0;
- }
-#endif /* CPU_ARM9 */
#if defined(CPU_ARM9E) || defined(CPU_ARM10)
if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM1026EJS) {
cpufuncs = armv5_ec_cpufuncs;
@@ -1130,37 +1054,6 @@ set_cpufuncs()
* CPU Setup code
*/
-#ifdef CPU_ARM9
-void
-arm9_setup()
-{
- int cpuctrl, cpuctrlmask;
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
- | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_AFLT_ENABLE;
- cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
- | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
- | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
- | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
- | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
- | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_VECRELOC
- | CPU_CONTROL_ROUNDROBIN;
-
- if (vector_page == ARM_VECTORS_HIGH)
- cpuctrl |= CPU_CONTROL_VECRELOC;
-
- /* Clear out the cache */
- cpu_idcache_wbinv_all();
-
- /* Set the control register */
- curcpu()->ci_ctrl = cpuctrl;
- cpu_control(cpuctrlmask, cpuctrl);
-
-}
-#endif /* CPU_ARM9 */
-
#if defined(CPU_ARM9E) || defined(CPU_ARM10)
void
arm9e_setup()
diff --git sys/arch/arm/arm/cpufunc_asm_arm9.S
sys/arch/arm/arm/cpufunc_asm_arm9.S
deleted file mode 100644
index 7864d09..0000000
--- sys/arch/arm/arm/cpufunc_asm_arm9.S
+++ /dev/null
@@ -1,254 +0,0 @@
-/* $OpenBSD: cpufunc_asm_arm9.S,v 1.1 2008/09/11 02:38:14 kevlo Exp $
*/
-/* $NetBSD: cpufunc_asm_arm9.S,v 1.6 2007/10/17 19:53:29 garbled Exp $
*/
-
-/*
- * Copyright (c) 2001, 2004 ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the company may not be used to endorse or promote
- * products derived from this software without specific prior written
- * permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * ARM9 assembly functions for CPU / MMU / TLB specific operations
- */
-
-#include <machine/cpu.h>
-#include <machine/asm.h>
-
-/*
- * Functions to set the MMU Translation Table Base register
- *
- * We need to clean and flush the cache as it uses virtual
- * addresses that are about to change.
- */
-ENTRY(arm9_setttb)
- stmfd sp!, {r0, lr}
- bl _C_LABEL(arm9_idcache_wbinv_all)
- ldmfd sp!, {r0, lr}
-
- mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
-
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
- mov pc, lr
-
-/*
- * TLB functions
- */
-ENTRY(arm9_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
- mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
- mov pc, lr
-
-/*
- * Cache operations. For the entire cache we use the set/index
- * operations.
- */
- s_max .req r0
- i_max .req r1
- s_inc .req r2
- i_inc .req r3
-
-ENTRY_NP(arm9_icache_sync_range)
- ldr ip, .Larm9_line_size
- cmp r1, #0x4000
- bcs .Larm9_icache_sync_all
- ldr ip, [ip]
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larm9_sync_next:
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl .Larm9_sync_next
- mov pc, lr
-
-ENTRY_NP(arm9_icache_sync_all)
-.Larm9_icache_sync_all:
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache cleaning code.
- */
- mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
- /* Fall through to clean Dcache. */
-
-.Larm9_dcache_wb:
- ldr ip, .Larm9_cache_data
- ldmia ip, {s_max, i_max, s_inc, i_inc}
-.Lnext_set:
- orr ip, s_max, i_max
-.Lnext_index:
- mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
- sub ip, ip, i_inc
- tst ip, i_max /* Index 0 is last one */
- bne .Lnext_index /* Next index */
- mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
- subs s_max, s_max, s_inc
- bpl .Lnext_set /* Next set */
- mov pc, lr
-
-.Larm9_line_size:
- .word _C_LABEL(arm_pdcache_line_size)
-
-ENTRY(arm9_dcache_wb_range)
- ldr ip, .Larm9_line_size
- cmp r1, #0x4000
- bcs .Larm9_dcache_wb
- ldr ip, [ip]
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larm9_wb_next:
- mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl .Larm9_wb_next
- mov pc, lr
-
-ENTRY(arm9_dcache_wbinv_range)
- ldr ip, .Larm9_line_size
- cmp r1, #0x4000
- bcs .Larm9_dcache_wbinv_all
- ldr ip, [ip]
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larm9_wbinv_next:
- mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl .Larm9_wbinv_next
- mov pc, lr
-
-/*
- * Note, we must not invalidate everything. If the range is too big we
- * must use wb-inv of the entire cache.
- */
-ENTRY(arm9_dcache_inv_range)
- ldr ip, .Larm9_line_size
- cmp r1, #0x4000
- bcs .Larm9_dcache_wbinv_all
- ldr ip, [ip]
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larm9_inv_next:
- mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl .Larm9_inv_next
- mov pc, lr
-
-ENTRY(arm9_idcache_wbinv_range)
- ldr ip, .Larm9_line_size
- cmp r1, #0x4000
- bcs .Larm9_idcache_wbinv_all
- ldr ip, [ip]
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-.Larm9_id_wbinv_next:
- mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
- mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl .Larm9_id_wbinv_next
- mov pc, lr
-
-ENTRY_NP(arm9_idcache_wbinv_all)
-.Larm9_idcache_wbinv_all:
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache purging code.
- */
- mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
- /* Fall through to purge Dcache. */
-
-ENTRY(arm9_dcache_wbinv_all)
-.Larm9_dcache_wbinv_all:
- ldr ip, .Larm9_cache_data
- ldmia ip, {s_max, i_max, s_inc, i_inc}
-.Lnext_set_inv:
- orr ip, s_max, i_max
-.Lnext_index_inv:
- mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
- sub ip, ip, i_inc
- tst ip, i_max /* Index 0 is last one */
- bne .Lnext_index_inv /* Next index */
- mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
- subs s_max, s_max, s_inc
- bpl .Lnext_set_inv /* Next set */
- mov pc, lr
-
-.Larm9_cache_data:
- .word _C_LABEL(arm9_dcache_sets_max)
-
-/*
- * Context switch.
- *
- * These is the CPU-specific parts of the context switcher cpu_switch()
- * These functions actually perform the TTB reload.
- */
-ENTRY(arm9_context_switch)
- /*
- * We can assume that the caches will only contain kernel addresses
- * at this point. So no need to flush them again.
- */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
-
- /* Paranoia -- make sure the pipeline is empty. */
- nop
- nop
- nop
- mov pc, lr
-
- .bss
-
-/* XXX The following macros should probably be moved to asm.h */
-#define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
-#define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
-
-/*
- * Parameters for the cache cleaning code. Note that the order of these
- * four variables is assumed in the code above. Hence the reason for
- * declaring them in the assembler file.
- */
- .align 0
-C_OBJECT(arm9_dcache_sets_max)
- .space 4
-C_OBJECT(arm9_dcache_index_max)
- .space 4
-C_OBJECT(arm9_dcache_sets_inc)
- .space 4
-C_OBJECT(arm9_dcache_index_inc)
- .space 4
diff --git sys/arch/arm/arm/pmap.c sys/arch/arm/arm/pmap.c
index 627f4d5..cd16005 100644
--- sys/arch/arm/arm/pmap.c
+++ sys/arch/arm/arm/pmap.c
@@ -4438,27 +4438,6 @@ pmap_pte_init_generic(void)
pmap_copy_page_func = pmap_copy_page_generic;
pmap_zero_page_func = pmap_zero_page_generic;
}
-
-#if defined(CPU_ARM9)
-void
-pmap_pte_init_arm9(void)
-{
-
- /*
- * ARM9 is compatible with generic, but we want to use
- * write-through caching for now.
- */
- pmap_pte_init_generic();
-
- pte_l1_s_cache_mode = L1_S_C;
- pte_l2_l_cache_mode = L2_C;
- pte_l2_s_cache_mode = L2_C;
-
- pte_l1_s_cache_mode_pt = L1_S_C;
- pte_l2_l_cache_mode_pt = L2_C;
- pte_l2_s_cache_mode_pt = L2_C;
-}
-#endif /* CPU_ARM9 */
#endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
#if defined(CPU_ARM10)
diff --git sys/arch/arm/conf/files.arm sys/arch/arm/conf/files.arm
index 857e7e6..91f8470 100644
--- sys/arch/arm/conf/files.arm
+++ sys/arch/arm/conf/files.arm
@@ -39,10 +39,8 @@ file arch/arm/arm/bcopyinout.S
file arch/arm/arm/copystr.S
file arch/arm/arm/cpufunc.c
file arch/arm/arm/cpufunc_asm.S
-file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9
file arch/arm/arm/cpufunc_asm_arm10.S cpu_arm9e | cpu_arm10
-file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_arm9e |
- cpu_arm10 |
+file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9e | cpu_arm10 |
cpu_sa110 |
cpu_sa1100 |
cpu_sa1110 |
diff --git sys/arch/arm/include/armreg.h sys/arch/arm/include/armreg.h
index f2a5854..cf05f71 100644
--- sys/arch/arm/include/armreg.h
+++ sys/arch/arm/include/armreg.h
@@ -176,10 +176,7 @@
#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */
/* Post-ARM7 CPUs */
-#define CPU_ID_ARM920T 0x41129200
-#define CPU_ID_ARM922T 0x41029220
#define CPU_ID_ARM926EJS 0x41069260
-#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
@@ -190,7 +187,6 @@
#define CPU_ID_ARM1136JSR1 0x4117b360
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
-#define CPU_ID_TI925T 0x54029250
#define CPU_ID_SA1110 0x6901b110
#define CPU_ID_IXP1200 0x6901c120
#define CPU_ID_80200 0x69052000
diff --git sys/arch/arm/include/cpuconf.h sys/arch/arm/include/cpuconf.h
index 6ed95ee..a770770 100644
--- sys/arch/arm/include/cpuconf.h
+++ sys/arch/arm/include/cpuconf.h
@@ -48,8 +48,7 @@
/*
* Determine which ARM architecture versions are configured.
*/
-#if (defined(CPU_ARM9) || \
- defined(CPU_SA1100) || defined(CPU_SA1110) || \
+#if (defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
#define ARM_ARCH_4 1
#else
@@ -91,8 +90,8 @@
* protection is not used, TEX/AP is used instead.
*/
-#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \
- defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARMv7) )
+#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+ defined(CPU_ARM11) || defined(CPU_ARMv7) )
#define ARM_MMU_GENERIC 1
#else
#define ARM_MMU_GENERIC 0
diff --git sys/arch/arm/include/cpufunc.h sys/arch/arm/include/cpufunc.h
index 416248a..25162f8 100644
--- sys/arch/arm/include/cpufunc.h
+++ sys/arch/arm/include/cpufunc.h
@@ -250,32 +250,6 @@ void sa1_cache_syncI_rng (vaddr_t start, vsize_t
end);
#endif
-#ifdef CPU_ARM9
-void arm9_setttb (u_int);
-
-void arm9_tlb_flushID_SE (u_int);
-
-void arm9_icache_sync_all (void);
-void arm9_icache_sync_range (vaddr_t, vsize_t);
-
-void arm9_dcache_wbinv_all (void);
-void arm9_dcache_wbinv_range (vaddr_t, vsize_t);
-void arm9_dcache_inv_range (vaddr_t, vsize_t);
-void arm9_dcache_wb_range (vaddr_t, vsize_t);
-
-void arm9_idcache_wbinv_all (void);
-void arm9_idcache_wbinv_range (vaddr_t, vsize_t);
-
-void arm9_context_switch (u_int);
-
-void arm9_setup (void);
-
-extern unsigned arm9_dcache_sets_max;
-extern unsigned arm9_dcache_sets_inc;
-extern unsigned arm9_dcache_index_max;
-extern unsigned arm9_dcache_index_inc;
-#endif
-
#if defined(CPU_ARM9E) || defined(CPU_ARM10)
void arm10_tlb_flushID_SE (u_int);
void arm10_tlb_flushI_SE (u_int);
@@ -377,7 +351,7 @@ extern unsigned armv7_dcache_index_inc;
#endif
-#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
+#if defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
diff --git sys/arch/arm/include/pmap.h sys/arch/arm/include/pmap.h
index 3851abb..eca0376 100644
--- sys/arch/arm/include/pmap.h
+++ sys/arch/arm/include/pmap.h
@@ -371,9 +371,6 @@ void pmap_copy_page_generic(struct vm_page *, struct
vm_page *);
void pmap_zero_page_generic(struct vm_page *);
void pmap_pte_init_generic(void);
-#if defined(CPU_ARM9)
-void pmap_pte_init_arm9(void);
-#endif /* CPU_ARM9 */
#if defined(CPU_ARM10)
void pmap_pte_init_arm10(void);
#endif /* CPU_ARM10 */
