Adapt FreeBSD's sysreg.h definitions for cp14/cp15 and make use of it in .S files.
Matched and changed by a script, verified to cause no binary change with armv7, armish, and zaurus kernels. Index: arm/arm/bcopyinout.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/bcopyinout.S,v retrieving revision 1.4 diff -u -p -r1.4 bcopyinout.S --- arm/arm/bcopyinout.S 4 Apr 2016 09:13:44 -0000 1.4 +++ arm/arm/bcopyinout.S 10 Apr 2016 12:41:00 -0000 @@ -39,6 +39,7 @@ #include "assym.h" #include <machine/asm.h> +#include <arm/sysreg.h> #ifdef __XSCALE__ #include "bcopyinout_xscale.S" @@ -85,7 +86,7 @@ ENTRY(copyin) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r4, c13, c0, 4 + mrc CP15_TPIDRPRW(r4) #else ldr r4, .Lcpu_info_primary #endif @@ -304,7 +305,7 @@ ENTRY(copyout) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r4, c13, c0, 4 + mrc CP15_TPIDRPRW(r4) #else ldr r4, .Lcpu_info_primary #endif @@ -513,7 +514,7 @@ ENTRY(kcopy) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r4, c13, c0, 4 + mrc CP15_TPIDRPRW(r4) #else ldr r4, .Lcpu_info_primary #endif @@ -701,7 +702,7 @@ ENTRY(kcopy) ENTRY(badaddr_read_1) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r2, c13, c0, 4 + mrc CP15_TPIDRPRW(r2) #else ldr r2, .Lcpu_info_primary #endif @@ -730,7 +731,7 @@ ENTRY(badaddr_read_1) ENTRY(badaddr_read_2) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r2, c13, c0, 4 + mrc CP15_TPIDRPRW(r2) #else ldr r2, .Lcpu_info_primary #endif @@ -759,7 +760,7 @@ ENTRY(badaddr_read_2) ENTRY(badaddr_read_4) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r2, c13, c0, 4 + mrc CP15_TPIDRPRW(r2) #else ldr r2, .Lcpu_info_primary #endif Index: arm/arm/copystr.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/copystr.S,v retrieving revision 1.5 diff -u -p -r1.5 copystr.S --- arm/arm/copystr.S 4 Apr 2016 09:13:44 -0000 1.5 +++ arm/arm/copystr.S 10 Apr 2016 12:41:00 -0000 @@ -41,6 +41,7 @@ #include "assym.h" #include <machine/asm.h> +#include <arm/sysreg.h> #include <sys/errno.h> .text @@ -106,7 +107,7 @@ ENTRY(copyinstr) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r4, c13, c0, 4 + mrc CP15_TPIDRPRW(r4) #else ldr r4, .Lcpu_info_primary #endif @@ -158,7 +159,7 @@ ENTRY(copyoutstr) #ifdef CPU_ARMv7 /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r4, c13, c0, 4 + mrc CP15_TPIDRPRW(r4) #else ldr r4, .Lcpu_info_primary #endif Index: arm/arm/cpufunc_asm.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm.S,v retrieving revision 1.3 diff -u -p -r1.3 cpufunc_asm.S --- arm/arm/cpufunc_asm.S 3 Apr 2016 13:55:23 -0000 1.3 +++ arm/arm/cpufunc_asm.S 10 Apr 2016 12:41:01 -0000 @@ -44,6 +44,7 @@ #include <machine/cpu.h> #include <machine/asm.h> +#include <arm/sysreg.h> .text .align 0 @@ -62,31 +63,31 @@ ENTRY(cpufunc_nullop) */ ENTRY(cpufunc_id) - mrc p15, 0, r0, c0, c0, 0 + mrc CP15_MIDR(r0) mov pc, lr ENTRY(cpu_get_control) - mrc p15, 0, r0, c1, c0, 0 + mrc CP15_SCTLR(r0) mov pc, lr ENTRY(cpu_read_cache_config) - mrc p15, 0, r0, c0, c0, 1 + mrc CP15_CTR(r0) mov pc, lr ENTRY(cpufunc_dfsr) - mrc p15, 0, r0, c5, c0, 0 + mrc CP15_DFSR(r0) mov pc, lr ENTRY(cpufunc_dfar) - mrc p15, 0, r0, c6, c0, 0 + mrc CP15_DFAR(r0) mov pc, lr ENTRY(cpufunc_ifsr) - mrc p15, 0, r0, c5, c0, 1 + mrc CP15_IFSR(r0) mov pc, lr ENTRY(cpufunc_ifar) - mrc p15, 0, r0, c6, c0, 2 + mrc CP15_IFAR(r0) mov pc, lr @@ -103,12 +104,12 @@ ENTRY(cpufunc_ifar) #if 0 /* See below. */ ENTRY(cpufunc_control) - mcr p15, 0, r0, c1, c0, 0 + mcr CP15_SCTLR(r0) mov pc, lr #endif ENTRY(cpufunc_domains) - mcr p15, 0, r0, c3, c0, 0 + mcr CP15_DACR(r0) mov pc, lr /* @@ -122,22 +123,22 @@ ENTRY(cpufunc_domains) */ ENTRY(cpufunc_control) - mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ + mrc CP15_SCTLR(r3) /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there is a change */ - mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ + mcrne CP15_SCTLR(r2) /* Write new control register */ mov r0, r3 /* Return old value */ mov pc, lr ENTRY(cpufunc_auxcontrol) - mrc p15, 0, r3, c1, c0, 1 /* Read the aux control register */ + mrc CP15_ACTLR(r3) /* Read the aux control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there is a change */ - mcrne p15, 0, r2, c1, c0, 1 /* Write new aux control register */ + mcrne CP15_ACTLR(r2) /* Write new aux control register */ mov r0, r3 /* Return old value */ mov pc, lr Index: arm/arm/cpufunc_asm_armv4.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_armv4.S,v retrieving revision 1.1 diff -u -p -r1.1 cpufunc_asm_armv4.S --- arm/arm/cpufunc_asm_armv4.S 1 Feb 2004 05:09:48 -0000 1.1 +++ arm/arm/cpufunc_asm_armv4.S 10 Apr 2016 12:41:01 -0000 @@ -39,29 +39,30 @@ #include <machine/cpu.h> #include <machine/asm.h> +#include <arm/sysreg.h> /* * TLB functions */ ENTRY(armv4_tlb_flushID) - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ + mcr CP15_TLBIALL(r0) /* flush I+D tlb */ mov pc, lr ENTRY(armv4_tlb_flushI) - mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */ + mcr CP15_ITLBIALL /* flush I tlb */ mov pc, lr ENTRY(armv4_tlb_flushD) - mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ + mcr CP15_DTLBIALL /* flush D tlb */ mov pc, lr ENTRY(armv4_tlb_flushD_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ + mcr CP15_DTLBIMVA /* flush D tlb single entry */ mov pc, lr /* * Other functions */ ENTRY(armv4_drain_writebuf) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ mov pc, lr Index: arm/arm/cpufunc_asm_armv7.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_armv7.S,v retrieving revision 1.9 diff -u -p -r1.9 cpufunc_asm_armv7.S --- arm/arm/cpufunc_asm_armv7.S 4 Apr 2016 09:06:28 -0000 1.9 +++ arm/arm/cpufunc_asm_armv7.S 10 Apr 2016 12:41:01 -0000 @@ -17,6 +17,7 @@ #include <machine/cpu.h> #include <machine/asm.h> +#include <arm/sysreg.h> ENTRY(armv7_cpu_sleep) wfi @@ -31,20 +32,20 @@ ENTRY(armv7_drain_writebuf) * Function to read the MPCore base address */ ENTRY(armv7_periphbase) - mrc p15, 4, r0, c15, c0, 0 + mrc CP15_CBAR(r0) mov pc, lr /* * Functions to set the MMU Translation Table Base register */ ENTRY(armv7_setttb) - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_ICIALLU /* Flush I cache */ + mcr CP15_BPIALL /* Flush BP cache */ dsb sy isb sy - mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + mcr CP15_TTBR0(r0) /* load new TTB */ + mcr CP15_TLBIALL(r0) /* invalidate I+D TLBs */ dsb sy isb sy @@ -54,16 +55,16 @@ ENTRY(armv7_setttb) * TLB functions */ ENTRY(armv7_tlb_flushID_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ - mcr p15, 0, r0, c7, c5, 7 /* flush va from BP */ + mcr CP15_DTLBIMVA /* flush D tlb single entry */ + mcr CP15_ITLBIMVA /* flush I tlb single entry */ + mcr CP15_BPIMVA /* flush va from BP */ dsb sy isb sy mov pc, lr ENTRY(armv7_tlb_flushI_SE) - mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ - mcr p15, 0, r0, c7, c5, 7 /* flush va from BP */ + mcr CP15_ITLBIMVA /* flush I tlb single entry */ + mcr CP15_BPIMVA /* flush va from BP */ dsb sy isb sy mov pc, lr @@ -72,27 +73,27 @@ ENTRY(armv7_tlb_flushI_SE) * TLB functions */ ENTRY(armv7_tlb_flushID) - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_TLBIALL(r0) /* flush I+D tlb */ + mcr CP15_BPIALL /* Flush BP cache */ dsb sy isb sy mov pc, lr ENTRY(armv7_tlb_flushI) - mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */ - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_ITLBIALL /* flush I tlb */ + mcr CP15_BPIALL /* Flush BP cache */ dsb sy isb sy mov pc, lr ENTRY(armv7_tlb_flushD) - mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ + mcr CP15_DTLBIALL /* flush D tlb */ dsb sy isb sy mov pc, lr ENTRY(armv7_tlb_flushD_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ + mcr CP15_DTLBIMVA /* flush D tlb single entry */ dsb sy isb sy mov pc, lr @@ -124,12 +125,12 @@ ENTRY(armv7_icache_sync_range) add r1, r1, r2 bic r0, r0, r3 1: - mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */ - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ + mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */ + mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */ add r0, r0, ip subs r1, r1, ip bhi 1b - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_BPIALL /* Flush BP cache */ dsb sy isb sy mov pc, lr @@ -141,8 +142,8 @@ ENTRY(armv7_icache_sync_all) * dcache, so that we can safely flush the Icache and fall through * into the Dcache cleaning code. */ - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_ICIALLU /* Flush I cache */ + mcr CP15_BPIALL /* Flush BP cache */ isb sy mov pc, lr @@ -157,7 +158,7 @@ ENTRY(armv7_dcache_wb_range) add r1, r1, r2 bic r0, r0, r3 1: - mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ + mcr CP15_DCCMVAC(r0) /* Clean D cache SE with VA */ add r0, r0, ip subs r1, r1, ip bhi 1b @@ -176,13 +177,13 @@ ENTRY(armv7_idcache_wbinv_range) add r1, r1, r2 bic r0, r0, r3 1: - mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */ - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ + mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */ + mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */ + mcr CP15_CNTPCT(r0, c7), 1 /* Purge D cache SE with VA */ add r0, r0, ip subs r1, r1, ip bhi 1b - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_BPIALL /* Flush BP cache */ dsb sy isb sy mov pc, lr @@ -198,9 +199,9 @@ ENTRY(armv7_dcache_wbinv_range) add r1, r1, r2 bic r0, r0, r3 1: - mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */ - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */ + mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */ + mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */ + mcr CP15_CNTPCT(r0, c7), 1 /* Purge D cache SE with VA */ add r0, r0, ip subs r1, r1, ip bhi 1b @@ -219,9 +220,9 @@ ENTRY(armv7_dcache_inv_range) add r1, r1, r2 bic r0, r0, r3 1: - mcr p15, 0, r0, c7, c11, 1 /* Clean D cache SE with VA to PoU */ - mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ - mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */ + mcr CP15_DCCMVAU(r0) /* Clean D cache SE with VA to PoU */ + mcr CP15_ICIMVAU(r0) /* Invalidate I cache SE with VA */ + mcr CP15_DCIMVAC(r0) /* Invalidate D cache SE with VA */ add r0, r0, ip subs r1, r1, ip bhi 1b @@ -244,13 +245,13 @@ ENTRY(armv7_context_switch) * We can assume that the caches will only contain kernel addresses * at this point. So no need to flush them again. */ - mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ - mcr p15, 0, r0, c7, c5, 6 /* Flush BP cache */ + mcr CP15_ICIALLU /* Flush I cache */ + mcr CP15_BPIALL /* Flush BP cache */ dsb sy isb sy - mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ + mcr CP15_TTBR0(r0) /* set the new TTB */ + mcr CP15_TLBIALL(r0) /* and flush the I+D tlbs */ dsb sy isb sy mov pc, lr Index: arm/arm/cpufunc_asm_xscale.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/cpufunc_asm_xscale.S,v retrieving revision 1.7 diff -u -p -r1.7 cpufunc_asm_xscale.S --- arm/arm/cpufunc_asm_xscale.S 31 Jan 2016 00:14:50 -0000 1.7 +++ arm/arm/cpufunc_asm_xscale.S 10 Apr 2016 12:41:01 -0000 @@ -74,6 +74,7 @@ #include <machine/cpu.h> #include <machine/asm.h> +#include <arm/sysreg.h> /* * Size of the XScale core caches. @@ -90,14 +91,14 @@ sub pc, pc, #4 #define CPWAIT(tmp) \ - mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ + mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ #define CPWAIT_AND_RETURN_SHIFTER lsr #32 #define CPWAIT_AND_RETURN(tmp) \ - mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ + mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\ /* Wait for it to complete and branch to the return address */ \ sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER @@ -110,13 +111,13 @@ ENTRY(xscale_cpwait) * changes in the control register. */ ENTRY(xscale_control) - mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ + mrc CP15_SCTLR(r3) /* Read the control register */ bic r2, r3, r0 /* Clear bits */ eor r2, r2, r1 /* XOR bits */ teq r2, r3 /* Only write if there was a change */ - mcrne p15, 0, r0, c7, c5, 6 /* Invalidate the BTB */ - mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ + mcrne CP15_BPIALL /* Invalidate the BTB */ + mcrne CP15_SCTLR(r2) /* Write new control register */ mov r0, r3 /* Return old value */ CPWAIT_AND_RETURN(r1) @@ -134,21 +135,21 @@ ENTRY(xscale_setttb) stmfd sp!, {r0-r3, lr} bl _C_LABEL(xscale_cache_cleanID) - mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ - mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ + mcr CP15_ICIALLU /* invalidate I$ and BTB */ + mcr CP15_CP15DSB(r0) /* drain write and fill buffer */ CPWAIT(r0) ldmfd sp!, {r0-r3, lr} /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 + mcr CP15_TTBR0(r0) /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ + mcr CP15_TLBIALL(r0) /* invalidate I+D TLB */ /* The cleanID above means we only need to flush the I cache here */ - mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ + mcr CP15_ICIALLU /* invalidate I$ and BTB */ CPWAIT(r0) @@ -162,8 +163,8 @@ ENTRY(xscale_setttb) * TLB operations, because we expect a pmap_update() to follow. */ ENTRY(xscale_tlb_flushID_SE) - mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ - mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ + mcr CP15_DTLBIMVA /* flush D tlb single entry */ + mcr CP15_ITLBIMVA /* flush I tlb single entry */ mov pc, lr /* @@ -174,7 +175,7 @@ ENTRY(xscale_cache_flushID) CPWAIT_AND_RETURN(r0) ENTRY(xscale_cache_flushI) - mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ + mcr CP15_ICIALLU /* flush I cache */ CPWAIT_AND_RETURN(r0) ENTRY(xscale_cache_flushD) @@ -182,7 +183,7 @@ ENTRY(xscale_cache_flushD) CPWAIT_AND_RETURN(r0) ENTRY(xscale_cache_flushI_SE) - mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ + mcr CP15_ICIMVAU(r0) /* flush I cache single entry */ CPWAIT_AND_RETURN(r0) ENTRY(xscale_cache_flushD_SE) @@ -191,12 +192,12 @@ ENTRY(xscale_cache_flushD_SE) * before invalidate-dcache-line to an address, or dirty * bits will not be cleared in the dcache array. */ - mcr p15, 0, r0, c7, c10, 1 - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ + mcr CP15_DCCMVAC(r0) + mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ CPWAIT_AND_RETURN(r0) ENTRY(xscale_cache_cleanD_E) - mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ + mcr CP15_DCCMVAC(r0) /* clean D cache entry */ CPWAIT_AND_RETURN(r0) /* @@ -275,7 +276,7 @@ _C_LABEL(xscale_cache_clean_size): ENTRY_NP(xscale_cache_syncI) ENTRY_NP(xscale_cache_purgeID) - mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ + mcr CP15_ICIALLU /* flush I cache (D cleaned below) */ ENTRY_NP(xscale_cache_cleanID) ENTRY_NP(xscale_cache_purgeD) ENTRY(xscale_cache_cleanD) @@ -288,7 +289,7 @@ ENTRY(xscale_cache_cleanD) CPWAIT(r0) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT(r0) @@ -310,23 +311,23 @@ ENTRY(xscale_cache_clean_minidata) subs r1, r1, #32 bne 1b - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT_AND_RETURN(r1) ENTRY(xscale_cache_purgeID_E) - mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ + mcr CP15_DCCMVAC(r0) /* clean D cache entry */ CPWAIT(r1) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ + mcr CP15_ICIMVAU(r0) /* flush I cache single entry */ + mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ CPWAIT_AND_RETURN(r1) ENTRY(xscale_cache_purgeD_E) - mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ + mcr CP15_DCCMVAC(r0) /* clean D cache entry */ CPWAIT(r1) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ + mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ CPWAIT_AND_RETURN(r1) /* @@ -343,14 +344,14 @@ ENTRY(xscale_cache_cleanD_rng) add r1, r1, r2 bic r0, r0, #0x1f -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ +1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT_AND_RETURN(r0) @@ -362,16 +363,16 @@ ENTRY(xscale_cache_purgeID_rng) add r1, r1, r2 bic r0, r0, #0x1f -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ - mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ +1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */ + mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ + mcr CP15_ICIMVAU(r0) /* flush I cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT_AND_RETURN(r0) @@ -383,15 +384,15 @@ ENTRY(xscale_cache_purgeD_rng) add r1, r1, r2 bic r0, r0, #0x1f -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ +1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */ + mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT_AND_RETURN(r0) @@ -403,15 +404,15 @@ ENTRY(xscale_cache_syncI_rng) add r1, r1, r2 bic r0, r0, #0x1f -1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ - mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ +1: mcr CP15_DCCMVAC(r0) /* clean D cache entry */ + mcr CP15_ICIMVAU(r0) /* flush I cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b CPWAIT(r0) - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT_AND_RETURN(r0) @@ -423,12 +424,12 @@ ENTRY(xscale_cache_flushD_rng) add r1, r1, r2 bic r0, r0, #0x1f -1: mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ +1: mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ add r0, r0, #32 subs r1, r1, #32 bhi 1b - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ CPWAIT_AND_RETURN(r0) @@ -450,10 +451,10 @@ ENTRY(xscale_context_switch) */ /* Write the TTB */ - mcr p15, 0, r0, c2, c0, 0 + mcr CP15_TTBR0(r0) /* If we have updated the TTB we must flush the TLB */ - mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */ + mcr CP15_TLBIALL(r0) /* flush the I+D tlb */ CPWAIT_AND_RETURN(r0) Index: arm/arm/cpuswitch.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/cpuswitch.S,v retrieving revision 1.15 diff -u -p -r1.15 cpuswitch.S --- arm/arm/cpuswitch.S 31 Jan 2016 00:14:50 -0000 1.15 +++ arm/arm/cpuswitch.S 10 Apr 2016 12:41:01 -0000 @@ -83,6 +83,7 @@ #include <machine/frame.h> #include <machine/intr.h> #include <machine/asm.h> +#include <arm/sysreg.h> /* LINTSTUB: include <sys/param.h> */ @@ -337,7 +338,7 @@ ENTRY(cpu_switchto) cmp r7, #0 /* No need to fixup vector table? */ ldrne r2, [r7] /* But if yes, fetch current value */ ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ - mcr p15, 0, r1, c3, c0, 0 /* Update DACR for new context */ + mcr CP15_DACR(r1) /* Update DACR for new context */ cmpne r2, r0 /* Stuffing the same value? */ #ifndef PMAP_INCLUDE_PTE_SYNC strne r0, [r7] /* Nope, update it */ Index: arm/arm/cpuswitch7.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/cpuswitch7.S,v retrieving revision 1.6 diff -u -p -r1.6 cpuswitch7.S --- arm/arm/cpuswitch7.S 4 Apr 2016 09:13:44 -0000 1.6 +++ arm/arm/cpuswitch7.S 10 Apr 2016 12:41:01 -0000 @@ -83,6 +83,7 @@ #include <machine/frame.h> #include <machine/intr.h> #include <machine/asm.h> +#include <arm/sysreg.h> /* LINTSTUB: include <sys/param.h> */ @@ -160,7 +161,7 @@ ENTRY(cpu_switchto) stmfd sp!, {r4-r7, lr} /* Get curcpu from TPIDRPRW. */ - mrc p15, 0, r3, c13, c0, 4 + mrc CP15_TPIDRPRW(r3) #ifdef MULTIPROCESSOR str r3, [r1, #(P_CPU)] #else @@ -286,7 +287,7 @@ ENTRY(cpu_switchto) cmp r7, #0 /* No need to fixup vector table? */ ldrne r2, [r7] /* But if yes, fetch current value */ ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ - mcr p15, 0, r1, c3, c0, 0 /* Update DACR for new context */ + mcr CP15_DACR(r1) /* Update DACR for new context */ cmpne r2, r0 /* Stuffing the same value? */ #ifndef PMAP_INCLUDE_PTE_SYNC strne r0, [r7] /* Nope, update it */ Index: arm/arm/irq_dispatch.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/irq_dispatch.S,v retrieving revision 1.10 diff -u -p -r1.10 irq_dispatch.S --- arm/arm/irq_dispatch.S 4 Apr 2016 09:13:44 -0000 1.10 +++ arm/arm/irq_dispatch.S 10 Apr 2016 12:41:01 -0000 @@ -71,6 +71,7 @@ #include "assym.h" #include <machine/asm.h> +#include <arm/sysreg.h> #include <machine/cpu.h> #include <machine/frame.h> #include <machine/intr.h> @@ -106,7 +107,7 @@ ASENTRY_NP(irq_entry) * r6 old value of curcpu()->ci_idepth */ #ifdef CPU_ARMv7 - mrc p15, 0, r5, c13, c0, 4 /* Get curcpu from TPIDRPRW. */ + mrc CP15_TPIDRPRW(r5) /* Get curcpu from TPIDRPRW. */ #else ldr r5, .Lcpu_info_primary #endif Index: arm/arm/locore.S =================================================================== RCS file: /cvs/src/sys/arch/arm/arm/locore.S,v retrieving revision 1.9 diff -u -p -r1.9 locore.S --- arm/arm/locore.S 4 Apr 2016 09:13:44 -0000 1.9 +++ arm/arm/locore.S 10 Apr 2016 12:41:01 -0000 @@ -36,6 +36,7 @@ #include <sys/syscall.h> #include <sys/errno.h> #include <machine/asm.h> +#include <arm/sysreg.h> #include <machine/cpu.h> #include <machine/frame.h> @@ -59,7 +60,7 @@ ASENTRY_NP(start) ldmia r1, {r1, r2, r8, sp} /* Set initial stack and */ #ifdef CPU_ARMv7 - mcr p15, 0, r8, c13, c0, 4 /* put curcpu into the TPIDRPRW */ + mcr CP15_TPIDRPRW(r8) /* put curcpu into the TPIDRPRW */ #endif sub r2, r2, r1 /* get zero init data */ @@ -141,8 +142,8 @@ ENTRY_NP(cpu_reset) * Hurl ourselves into the ROM */ mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) - mcr p15, 0, r0, c1, c0, 0 - mcrne p15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ + mcr CP15_SCTLR(r0) + mcrne CP15_TLBIALL(r2) /* nail I+D TLB on ARMv4 and greater */ mov pc, r4 /* Index: arm/xscale/pxa2x0_apm_asm.S =================================================================== RCS file: /cvs/src/sys/arch/arm/xscale/pxa2x0_apm_asm.S,v retrieving revision 1.5 diff -u -p -r1.5 pxa2x0_apm_asm.S --- arm/xscale/pxa2x0_apm_asm.S 31 Jan 2016 00:14:50 -0000 1.5 +++ arm/xscale/pxa2x0_apm_asm.S 10 Apr 2016 12:41:02 -0000 @@ -17,6 +17,7 @@ */ #include <machine/asm.h> +#include <arm/sysreg.h> #include <machine/cpu.h> #include <arch/arm/xscale/pxa2x0reg.h> @@ -147,19 +148,19 @@ ENTRY(pxa2x0_cpu_suspend) ldr r2, =pxa2x0_cpu_resume_virt str r2, [r3], #4 - mrc p15, 0, r2, c1, c0, 0 /* Load MMU control register. */ + mrc CP15_SCTLR(r2) /* Load MMU control register. */ mov r0, #0xff000000 orr r0, r0, #0x00ff0000 bic r2, r2, r0 /* Clear undefined bits. */ str r2, [r3], #4 /* Save MMU control register. */ - mrc p15, 0, r2, c2, c0, 0 /* Load TTB address. */ + mrc CP15_TTBR0(r2) /* Load TTB address. */ mov r0, #0x00003f00 orr r0, r0, #0x000000ff bic r2, r2, r0 /* Clear undefined bits. */ str r2, [r3], #4 /* Save TTB address. */ - mrc p15, 0, r2, c3, c0, 0 /* Load domain access control. */ + mrc CP15_DACR(r2) /* Load domain access control. */ str r2, [r3], #4 /* Save domain access control. */ mrs r2, spsr /* Load SVC saved CPSR. */ @@ -196,7 +197,7 @@ ENTRY(pxa2x0_cpu_suspend) /* At this point all critical registers have been saved. */ mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ mov r1, #DCACHE_CACHELINECOUNT ldr r2, .Lxscale_cache_clean_addr @@ -215,7 +216,7 @@ cache_flush_loop: msr cpsr_c, r2 /* disable IRQ/FIQ */ mcr p15, 0, r0, c7, c2, 5 /* allocate cache line */ - mcr p15, 0, r0, c7, c6, 1 /* flush D cache single entry */ + mcr CP15_DCIMVAC(r0) /* flush D cache single entry */ mrs r2, cpsr and r2, r2, #~(PSR_I|PSR_F) @@ -226,7 +227,7 @@ cache_flush_loop: bne cache_flush_loop mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ + mcr CP15_CP15DSB(r0) /* drain write buffer */ b 1f 1: @@ -305,11 +306,11 @@ ENTRY(pxa2x0_cpu_resume) ldr r0, .Lsleepdata_phys /* Point to PA of saved data. */ ldmia r0!, {r7-r10} - mcr p15, 0, r10, c3, c0, 0 /* Restore domain access control. */ - mcr p15, 0, r9, c2, c0, 0 /* Restore TTB address. */ - mcr p15, 0, r0, c8, c7, 0 /* Flush I+D TLBs. */ + mcr CP15_DACR(r10) /* Restore domain access control. */ + mcr CP15_TTBR0(r9) /* Restore TTB address. */ + mcr CP15_TLBIALL(r0) /* Flush I+D TLBs. */ mcr p15, 0, r0, c7, c7, 0 /* Flush I+D BTB. */ - mcr p15, 0, r8, c1, c0, 0 /* Restore MMU control. */ + mcr CP15_SCTLR(r8) /* Restore MMU control. */ mov pc, r7 /* Jump to virtual address. */ nop nop Index: armish/armish/armish_start.S =================================================================== RCS file: /cvs/src/sys/arch/armish/armish/armish_start.S,v retrieving revision 1.2 diff -u -p -r1.2 armish_start.S --- armish/armish/armish_start.S 29 May 2006 17:30:26 -0000 1.2 +++ armish/armish/armish_start.S 10 Apr 2016 12:41:02 -0000 @@ -37,6 +37,7 @@ */ #include <machine/asm.h> +#include <arm/sysreg.h> #include <arm/armreg.h> #include <arm/pte.h> @@ -55,9 +56,9 @@ _C_LABEL(iq80321_start): bic r8, r8, #0xff000000 /* clear upper 8 bits */ orr r8, r8, #0xa0000000 /* OR in physical base address */ - mrc p15, 0, r2, c1, c0, 0 + mrc CP15_SCTLR(r2) bic r2, r2, #CPU_CONTROL_MMU_ENABLE - mcr p15, 0, r2, c1, c0, 0 + mcr CP15_SCTLR(r2) nop nop @@ -118,29 +119,29 @@ Lunmapped: /* OK! Page table is set up. Give it to the CPU. */ adr r0, Ltable ldr r0, [r0] - mcr p15, 0, r0, c2, c0, 0 + mcr CP15_TTBR0(r0) /* Flush the old TLBs, just in case. */ - mcr p15, 0, r0, c8, c7, 0 + mcr CP15_TLBIALL(r0) /* Set the Domain Access register. Very important! */ mov r0, #1 - mcr p15, 0, r0, c3, c0, 0 + mcr CP15_DACR(r0) /* Get ready to jump to the "real" kernel entry point... */ ldr r0, Lstart /* OK, let's enable the MMU. */ - mrc p15, 0, r2, c1, c0, 0 + mrc CP15_SCTLR(r2) orr r2, r2, #CPU_CONTROL_MMU_ENABLE - mcr p15, 0, r2, c1, c0, 0 + mcr CP15_SCTLR(r2) nop nop nop /* CPWAIT sequence to make sure the MMU is on... */ - mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ + mrc CP15_TTBR0(r2) /* arbitrary read of CP15 */ mov r2, r2 /* force it to complete */ mov pc, r0 /* leap to kernel entry point! */ Index: armv7/armv7/armv7_start.S =================================================================== RCS file: /cvs/src/sys/arch/armv7/armv7/armv7_start.S,v retrieving revision 1.5 diff -u -p -r1.5 armv7_start.S --- armv7/armv7/armv7_start.S 31 Jan 2016 00:14:50 -0000 1.5 +++ armv7/armv7/armv7_start.S 10 Apr 2016 12:41:02 -0000 @@ -31,6 +31,7 @@ */ #include <machine/asm.h> +#include <arm/sysreg.h> #include <arm/armreg.h> #include <arm/pte.h> @@ -50,7 +51,7 @@ sub pc, pc, #4 #define CPWAIT(tmp) \ - mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ + mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ @@ -146,17 +147,17 @@ _C_LABEL(bootstrap_start): cmp r1, #0 bne 2b - mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ - mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ + mcr CP15_TTBR0(r0) /* Set TTB */ + mcr CP15_TLBIALL(r0) /* Flush TLB */ /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) - mcr p15, 0, r0, c3, c0, 0 + mcr CP15_DACR(r0) /* Enable MMU */ - mrc p15, 0, r0, c1, c0, 0 + mrc CP15_SCTLR(r0) orr r0, r0, #CPU_CONTROL_MMU_ENABLE - mcr p15, 0, r0, c1, c0, 0 + mcr CP15_SCTLR(r0) CPWAIT(r0) /* Restore U-Boot arguments */ Index: zaurus/zaurus/zaurus_start.S =================================================================== RCS file: /cvs/src/sys/arch/zaurus/zaurus/zaurus_start.S,v retrieving revision 1.3 diff -u -p -r1.3 zaurus_start.S --- zaurus/zaurus/zaurus_start.S 12 Feb 2014 05:31:58 -0000 1.3 +++ zaurus/zaurus/zaurus_start.S 10 Apr 2016 12:41:05 -0000 @@ -31,6 +31,7 @@ */ #include <machine/asm.h> +#include <arm/sysreg.h> #include <arm/armreg.h> #include <arm/pte.h> @@ -51,7 +52,7 @@ sub pc, pc, #4 #define CPWAIT(tmp) \ - mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ + mrc CP15_TTBR0(tmp) /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ @@ -107,12 +108,12 @@ zaurus_start_ram: * in VA 0xc0200000.. */ - mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */ + mrc CP15_TTBR0(r0) /* get ttb prepared by redboot */ adr r4, mmu_init_table2 #define BUILD_STARTUP_PAGETABLE #ifdef BUILD_STARTUP_PAGETABLE - mrc p15, 0, r2, c1, c0, 0 + mrc CP15_SCTLR(r2) mov r2, #0 tst r2, #CPU_CONTROL_MMU_ENABLE /* we already have a page table? */ bne 3f @@ -134,17 +135,17 @@ zaurus_start_ram: bne 2b #endif - mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ - mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ + mcr CP15_TTBR0(r0) /* Set TTB */ + mcr CP15_TLBIALL(r0) /* Flush TLB */ /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) - mcr p15, 0, r0, c3, c0, 0 + mcr CP15_DACR(r0) /* Enable MMU */ - mrc p15, 0, r0, c1, c0, 0 + mrc CP15_SCTLR(r0) orr r0, r0, #CPU_CONTROL_MMU_ENABLE - mcr p15, 0, r0, c1, c0, 0 + mcr CP15_SCTLR(r0) CPWAIT(r0) /* Jump to kernel code in TRUE VA */ --- /dev/null Mon Apr 11 03:01:47 2016 +++ arm/include/sysreg.h Mon Apr 11 03:01:34 2016 @@ -0,0 +1,272 @@ +/* $OpenBSD$ */ +/*- + * Copyright 2014 Svatopluk Kraus <onw...@gmail.com> + * Copyright 2014 Michal Meloun <mel...@miracle.cz> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: head/sys/arm/include/sysreg.h 294740 2016-01-25 18:02:28Z zbb $ + */ + +/* + * Macros to make working with the System Control Registers simpler. + * + * Note that when register r0 is hard-coded in these definitions it means the + * cp15 operation neither reads nor writes the register, and r0 is used only + * because some syntatically-valid register name has to appear at that point to + * keep the asm parser happy. + */ + +#ifndef MACHINE_SYSREG_H +#define MACHINE_SYSREG_H + +/* + * CP14 registers + */ + +#define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */ +#define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */ +#define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */ +#define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */ +#define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */ +#define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */ +#define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */ +#define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */ + +#define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */ + + +/* + * CP15 C0 registers + */ +#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ +#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ +#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ +#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ +#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ +#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ + +#define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ +#define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ +#define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ +#define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ +#define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ +#define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ +#define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ +#define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ + +#define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ +#define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ +#define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ +#define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ +#define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ +#define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ + +#define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ +#define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ +#define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ + +#define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ + +/* + * CP15 C1 registers + */ +#define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ +#define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ +#define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ + +#define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ +#define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ +#define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ + +/* + * CP15 C2 registers + */ +#define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ +#define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ +#define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ + +/* + * CP15 C3 registers + */ +#define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ + +/* + * CP15 C5 registers + */ +#define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ + +/* From ARMv6: */ +#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ +/* From ARMv7: */ +#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ +#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ + +/* + * CP15 C6 registers + */ +#define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ + +/* From ARMv6k: */ +#define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ + +/* + * CP15 C7 registers + */ +#ifdef MULTIPROCESSOR +/* From ARMv7: */ +#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ +#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ +#endif + +#define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ + +#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ +#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ +#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ +#define CP15_BPIMVA p15, 0, r0, c7, c5, 7 /* Branch predictor invalidate by MVA */ + +#define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ +#define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ + +#define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ +#define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ +#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ +#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ + +/* From ARMv7: */ +#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ +#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ +#define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ +#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ + +#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ +#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ + +#define CP15_CP15DSB(rr) p15, 0, rr, c7, c10, 4 +#define CP15_CP15DMB(rr) p15, 0, rr, c7, c10, 5 + +/* From ARMv7: */ +#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ + +#define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ +#define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ + +/* + * CP15 C8 registers + */ +#ifdef MULTIPROCESSOR +/* From ARMv7: */ +#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ +#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ +#define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ +#define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ +#endif + +#define CP15_DTLBIALL p15, 0, r0, c8, c6, 0 /* flush D tlb */ +#define CP15_DTLBIMVA p15, 0, r0, c8, c6, 1 /* Invalidate D TLB by MVA */ +#define CP15_ITLBIALL p15, 0, r0, c8, c5, 0 /* flush I tlb */ +#define CP15_ITLBIMVA p15, 0, r0, c8, c5, 1 /* Invalidate I TLB by MVA */ + +#define CP15_TLBIALL(rr) p15, 0, rr, c8, c7, 0 /* Invalidate entire unified TLB */ +#define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ +#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ + +/* From ARMv6: */ +#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ + +/* + * CP15 C9 registers + */ +#define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */ +#define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */ +#define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */ +#define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */ +#define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */ +#define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */ +#define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */ +#define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */ +#define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */ +#define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */ +#define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */ +#define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */ +#define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */ + +/* + * CP15 C10 registers + */ +/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ +#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ +#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ +/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ +#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ +#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ + +#define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ +#define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ + +/* + * CP15 C12 registers + */ +#define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ +#define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ + +#define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ + +/* + * CP15 C13 registers + */ +#define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ +#define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ +#define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ +#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ +#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ + +/* + * CP15 C14 registers + * These are the Generic Timer registers and may be unallocated on some SoCs. + * Only use these when you know the Generic Timer is available. + */ +#define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */ +#define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */ +#define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */ +#define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */ +#define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */ +#define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */ +#define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */ +#define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */ +#define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */ +/* 64-bit registers for use with mcrr/mrrc */ +#define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */ +#define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */ +#define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */ +#define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */ +#define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ +#define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ + +/* + * CP15 C15 registers + */ +#define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */ + +#endif /* !MACHINE_SYSREG_H */