>
> To helpdebugging sdmmc problems, it would be useful if we printed a
> bit more information about the controller. The diff below does this,
> and this is whatitlooks like on the APU2.
>
> sdhc0 at pci0 dev 20 function 7 "AMD Bolton SD/MMC" rev 0x01: apic 4 int 16
> sdhc0: 63 MHz base clock
> sdmmc0 at sdhc0: 4-bit, sd high-speed, mmc high-speed, dma
>
> This tells me immediately why the transfer speeds on the APU2 are
> somewhat sub-optimal. The base clock rate means that maximum bus
> clock that can be used to access the SD card is 31.5 MHz instead of 50
> MHz, reducing the throughput to about 60% of the theoretical maximum.
>
> ok?
Ugh that diff also included bits to make your SD cards go at double
the speed.
Index: sdhc.c
===================================================================
RCS file: /cvs/src/sys/dev/sdmmc/sdhc.c,v
retrieving revision 1.48
diff -u -p -r1.48 sdhc.c
--- sdhc.c 1 May 2016 18:29:44 -0000 1.48
+++ sdhc.c 1 May 2016 19:23:49 -0000
@@ -209,6 +209,8 @@ sdhc_host_found(struct sdhc_softc *sc, b
goto err;
}
+ printf("%s: %d MHz base clock\n", DEVNAME(sc), hp->clkbase / 1000);
+
/*
* XXX Set the data timeout counter value according to
* capabilities. (2.2.15)
Index: sdmmc.c
===================================================================
RCS file: /cvs/src/sys/dev/sdmmc/sdmmc.c,v
retrieving revision 1.41
diff -u -p -r1.41 sdmmc.c
--- sdmmc.c 1 May 2016 16:04:39 -0000 1.41
+++ sdmmc.c 1 May 2016 19:23:49 -0000
@@ -98,6 +98,18 @@ sdmmc_attach(struct device *parent, stru
struct sdmmcbus_attach_args *saa = aux;
int error;
+ if (ISSET(saa->caps, SMC_CAPS_8BIT_MODE))
+ printf(": 8-bit");
+ else if (ISSET(saa->caps, SMC_CAPS_4BIT_MODE))
+ printf(": 4-bit");
+ else
+ printf(": 1-bit");
+ if (ISSET(saa->caps, SMC_CAPS_SD_HIGHSPEED))
+ printf(", sd high-speed");
+ if (ISSET(saa->caps, SMC_CAPS_MMC_HIGHSPEED))
+ printf(", mmc high-speed");
+ if (ISSET(saa->caps, SMC_CAPS_DMA))
+ printf(", dma");
printf("\n");
sc->sct = saa->sct;
