Greetings, Here follows some minor spelling fixes found in markdown files inside the gcc folder. Wanted something simple for my first patch.
Any insight or comments? Cheers, Carlos Index: gcc/config/alpha/alpha.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/alpha/alpha.md,v retrieving revision 1.3 diff -u -p -u -r1.3 alpha.md --- gcc/config/alpha/alpha.md 28 Nov 2012 20:46:15 -0000 1.3 +++ gcc/config/alpha/alpha.md 1 Mar 2017 16:25:50 -0000 @@ -124,7 +124,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi ;; The ROUND_SUFFIX attribute marks which instructions require a ;; rounding-mode suffix. The value NONE indicates no suffix, -;; the value NORMAL indicates a suffix controled by alpha_fprm. +;; the value NORMAL indicates a suffix controlled by alpha_fprm. (define_attr "round_suffix" "none,normal,c" (const_string "none")) @@ -137,7 +137,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) ;; -;; The actual suffix emitted is controled by alpha_fptm. +;; The actual suffix emitted is controlled by alpha_fptm. (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" (const_string "none")) Index: gcc/config/c4x/c4x.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/c4x/c4x.md,v retrieving revision 1.1.1.1 diff -u -p -u -r1.1.1.1 c4x.md --- gcc/config/c4x/c4x.md 29 Nov 2003 12:31:55 -0000 1.1.1.1 +++ gcc/config/c4x/c4x.md 1 Mar 2017 16:25:50 -0000 @@ -190,7 +190,7 @@ ; didn't allow it to move the CC around. ; Note that fundamental operations, such as moves, must not clobber the -; CC. Thus movqi choses a move instruction that doesn't clobber the CC. +; CC. Thus movqi chooses a move instruction that doesn't clobber the CC. ; If GCC wants to combine a move with a compare, it is smart enough to ; chose the move instruction that sets the CC. @@ -7313,7 +7313,7 @@ "stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++") -; The following two peepholes remove an unecessary load +; The following two peepholes remove an unnecessary load ; often found at the end of a function. These peepholes ; could be generalized to other binary operators. They shouldn't ; be required if we run a post reload mop-up pass. Index: gcc/config/fr30/fr30.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/fr30/fr30.md,v retrieving revision 1.1.1.1 diff -u -p -u -r1.1.1.1 fr30.md --- gcc/config/fr30/fr30.md 29 Nov 2003 12:32:16 -0000 1.1.1.1 +++ gcc/config/fr30/fr30.md 1 Mar 2017 16:25:50 -0000 @@ -639,7 +639,7 @@ ;; We need some trickery to be able to handle the addition of ;; large (ie outside +/- 16) constants. We need to be able to ;; handle this because reload assumes that it can generate add -;; instructions with arbitary sized constants. +;; instructions with arbitrary sized constants. (define_expand "addsi3" [(set (match_operand:SI 0 "register_operand" "") (plus:SI (match_operand:SI 1 "register_operand" "") Index: gcc/config/frv/frv.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/frv/frv.md,v retrieving revision 1.1.1.1 diff -u -p -u -r1.1.1.1 frv.md --- gcc/config/frv/frv.md 29 Nov 2003 12:32:27 -0000 1.1.1.1 +++ gcc/config/frv/frv.md 1 Mar 2017 16:25:51 -0000 @@ -463,7 +463,7 @@ first regular expression *and* the reservation described by the second regular expression *and* etc. - 4. "*" is used for convinience and simply means sequence in + 4. "*" is used for convenience and simply means sequence in which the regular expression are repeated NUMBER times with cycle advancing (see ","). Index: gcc/config/i386/i386.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/i386/i386.md,v retrieving revision 1.1.1.3 diff -u -p -u -r1.1.1.3 i386.md --- gcc/config/i386/i386.md 28 Nov 2012 20:41:38 -0000 1.1.1.3 +++ gcc/config/i386/i386.md 1 Mar 2017 16:25:52 -0000 @@ -1149,7 +1149,7 @@ (const_string "imov"))) (set_attr "mode" "SI,SI,SI,SI,DI,TI,SI,SI")]) -;; Stores and loads of ax to arbitary constant address. +;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "*movabssi_1_rex64" @@ -1267,7 +1267,7 @@ ] (const_string "HI")))]) -;; Stores and loads of ax to arbitary constant address. +;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "*movabshi_1_rex64" @@ -1598,7 +1598,7 @@ (const_string "SI") (const_string "QI")))]) -;; Stores and loads of ax to arbitary constant address. +;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "*movabsqi_1_rex64" @@ -1926,7 +1926,7 @@ (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*") (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI")]) -;; Stores and loads of ax to arbitary constant address. +;; Stores and loads of ax to arbitrary constant address. ;; We fake an second form of instruction to force reload to load address ;; into register when rax is not available (define_insn "*movabsdi_1_rex64" Index: gcc/config/m32r/m32r.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/m32r/m32r.md,v retrieving revision 1.1.1.1 diff -u -p -u -r1.1.1.1 m32r.md --- gcc/config/m32r/m32r.md 29 Nov 2003 12:33:21 -0000 1.1.1.1 +++ gcc/config/m32r/m32r.md 1 Mar 2017 16:25:52 -0000 @@ -2487,7 +2487,7 @@ if (! zero_and_one (operands [2], operands [3])) FAIL; - /* Generate the comparision that will set the carry flag. */ + /* Generate the comparison that will set the carry flag. */ operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0, m32r_compare_op1, TRUE); Index: gcc/config/mips/mips.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/mips/mips.md,v retrieving revision 1.3 diff -u -p -u -r1.3 mips.md --- gcc/config/mips/mips.md 28 Nov 2012 20:46:15 -0000 1.3 +++ gcc/config/mips/mips.md 1 Mar 2017 16:25:53 -0000 @@ -8049,7 +8049,7 @@ move\\t%0,%z4\\n\\ [(set_attr "type" "branch") (set_attr "mode" "none")]) -;; Conditional branch on equality comparision. +;; Conditional branch on equality comparison. (define_insn "branch_equality" [(set (pc) Index: gcc/config/sh/sh.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/sh/sh.md,v retrieving revision 1.2 diff -u -p -u -r1.2 sh.md --- gcc/config/sh/sh.md 25 Apr 2008 22:46:49 -0000 1.2 +++ gcc/config/sh/sh.md 1 Mar 2017 16:25:53 -0000 @@ -1253,7 +1253,7 @@ ; the udivsi3 libcall has the same name, we must consider all registers ; clobbered that are in the union of the registers clobbered by the ; shmedia and the shcompact implementation. Note, if the shcompact -; implemenation actually used shcompact code, we'd need to clobber +; implementation actually used shcompact code, we'd need to clobber ; also r23 and fr23. (define_insn "udivsi3_i1_media" [(set (match_operand:SI 0 "register_operand" "=z") @@ -1419,7 +1419,7 @@ ; the sdivsi3 libcall has the same name, we must consider all registers ; clobbered that are in the union of the registers clobbered by the ; shmedia and the shcompact implementation. Note, if the shcompact -; implemenation actually used shcompact code, we'd need to clobber +; implementation actually used shcompact code, we'd need to clobber ; also r22, r23 and fr23. (define_insn "divsi3_i1_media" [(set (match_operand:SI 0 "register_operand" "=z") Index: gcc/config/sparc/sparc.md =================================================================== RCS file: /cvs/src/gnu/usr.bin/gcc/gcc/config/sparc/sparc.md,v retrieving revision 1.3 diff -u -p -u -r1.3 sparc.md --- gcc/config/sparc/sparc.md 28 Nov 2012 20:46:15 -0000 1.3 +++ gcc/config/sparc/sparc.md 1 Mar 2017 16:25:54 -0000 @@ -3212,7 +3212,7 @@ operands[1])); } - /* Handle MEM cases first, note that only v9 guarentees + /* Handle MEM cases first, note that only v9 guarantees full 16-byte alignment for quads. */ if (GET_CODE (operands[0]) == MEM) {