On Mon, Sep 18, 2017 at 11:19:09AM +0100, Stuart Henderson wrote:
> On 2017/09/18 04:28, Artturi Alm wrote:
> > Do i really need to reference datasheets, or would someone explain to me
> > the value of this MSB robbing?
>
> I think, if you're proposing a change, you should explain why that
> change should be made, rather than asking others to defend the current
> situation..
>
guess i wasn't clear enough. of the 3 timers two are 64bit timers, of them
agtimer doesn't even support reading just 32bit, nor any of them do just
31bits as claimed by the timercounter mask.
so all of them act opposite to what's written in sys/timetc.h, the last bit
won't be constant with these.
amptimer's low register does have full 32bits, if it didn't, i doubt this
function could exist:
/sys/arch/arm/cortex/amptimer.c:
128 uint64_t
129 amptimer_readcnt64(struct amptimer_softc *sc)
130 {
131 uint32_t high0, high1, low;
132 bus_space_tag_t iot = sc->sc_iot;
133 bus_space_handle_t ioh = sc->sc_ioh;
134
135 do {
136 high0 = bus_space_read_4(iot, ioh, GTIMER_CNT_HIGH);
137 low = bus_space_read_4(iot, ioh, GTIMER_CNT_LOW);
138 high1 = bus_space_read_4(iot, ioh, GTIMER_CNT_HIGH);
139 } while (high0 != high1);
140
141 return ((((uint64_t)high1) << 32) | low);
142 }
if you google for "swpu223g" you'll find omap3430 technical reference manual
pdf, in it you can find the description of gptimer's TCRR register, at
page 2600, also it _will_ count beyond 0x7fffffff.
you can find reference to gptimer(missed replace) from amptimer.c, i guess
amptimer was where agtimer got it from, so maybe just an bad copy-paste.
-Artturi
