On 13/12/17 10:29, Martin Pieuchot wrote: > On 13/12/17(Wed) 09:54, David Gwynne wrote: >> im still looking at vlan performance problems, as discussed by mpi@ >> at http://www.grenadille.net/post/2017/02/13/What-happened-to-my-vlan. >> >> recently it occurred to me that we're making an implicit assumption >> that having the chip handle the injection of vlan tags has zero >> cost, and that all the loss in performance is purely a software >> problem. to test this assumption i knocked up the diff below to >> disable hw vlan tagging in ix(4), which was used in the tests mpi >> and hrvoje did. >> >> hrvoje tested this diff for me and noted a 10% improvement in pps >> when forwarding between vlan interfaces on ix(4). to quote hrvoje: >> >> without diff >> send - receive >> vlan - vlan = 830Kpps >> >> with diff >> send - receive >> vlan - vlan = 995Kpps >> >> my conclusion is that assumption that nics are fast at offloads is >> wrong. therefore id like to put this in. unfortunately 10% doesnt >> account for the entire loss in forwarding over vlan, but it does >> help a bit. >> >> would anyone else like to test? or ok it? > > I don't have hardware to test but I'd like to add that in bridge(4) > scenario hardware tagging also decrease performance. > > From my point of view removing this per-chip option makes the stack > simpler, so I'm all for it. However I'd like to hear more test reports > on different ix(4) models.
Sorry to jump in but it looks to me that apart from different ix(4) models this should also be checked with different CPUs as well. I mean that with a recent fast CPU like E5-26xx it seems you get an improvement. This might not be the case with an older CPU. Also what happens with L2 performance (not only L3 routing). best, G
