On Tue, Dec 26, 2017 at 05:12:39PM +1100, Jonathan Gray wrote:
>
> On Tue, Dec 26, 2017 at 01:15:35PM +0800, Kevin Lo wrote:
> > The diff below adds support for the "next-generation" clock and pinctrl
> > bindings for the Allwinner A33.
> >
> > Tested on my Banana Pi M2 Magic. dmesg: http://ix.io/DoB
> > ok?
> >
> > Index: sys/dev/fdt/ehci_fdt.c
> > ===================================================================
> > RCS file: /cvs/src/sys/dev/fdt/ehci_fdt.c,v
> > retrieving revision 1.2
> > diff -u -p -u -p -r1.2 ehci_fdt.c
> > --- sys/dev/fdt/ehci_fdt.c 17 Dec 2017 13:23:03 -0000 1.2
> > +++ sys/dev/fdt/ehci_fdt.c 25 Dec 2017 09:43:48 -0000
> > @@ -273,9 +273,10 @@ sun4i_phy_init(struct ehci_fdt_softc *sc
> >
> > /*
> > * We need to poke an undocumented register to make the PHY
> > - * work on Allwinner H3/H5/A64.
> > + * work on Allwinner H3/H5/A33/A64.
> > */
> > - if (OF_is_compatible(node, "allwinner,sun8i-h3-usb-phy") ||
> > + if (OF_is_compatible(node, "allwinner,sun8i-a33-usb-phy") ||
> > + OF_is_compatible(node, "allwinner,sun8i-h3-usb-phy") ||
> > OF_is_compatible(node, "allwinner,sun50i-a64-usb-phy")) {
> > val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
> > val &= ~(1 << 1);
>
> Is this actually required? U-Boot only does it for h3/h5.
>
> If so should "allwinner,sun8i-a23-usb-phy" and
> "allwinner,sun8i-v3s-usb-phy" also be added?
Thanks for catching this, it's not required. Here is an updated diff:
Index: sys/dev/fdt/sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.12
diff -u -p -u -p -r1.12 sxiccmu.c
--- sys/dev/fdt/sxiccmu.c 24 Dec 2017 18:24:06 -0000 1.12
+++ sys/dev/fdt/sxiccmu.c 26 Dec 2017 07:56:08 -0000
@@ -88,6 +88,8 @@ void sxiccmu_ccu_reset(void *, uint32_t
uint32_t sxiccmu_a10_get_frequency(struct sxiccmu_softc *, uint32_t);
int sxiccmu_a10_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_a23_get_frequency(struct sxiccmu_softc *, uint32_t);
+int sxiccmu_a23_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_a64_get_frequency(struct sxiccmu_softc *, uint32_t);
int sxiccmu_a64_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
uint32_t sxiccmu_a80_get_frequency(struct sxiccmu_softc *, uint32_t);
@@ -110,6 +112,8 @@ sxiccmu_match(struct device *parent, voi
OF_is_compatible(node, "allwinner,sun5i-a10s") ||
OF_is_compatible(node, "allwinner,sun5i-r8") ||
OF_is_compatible(node, "allwinner,sun7i-a20") ||
+ OF_is_compatible(node, "allwinner,sun8i-a23") ||
+ OF_is_compatible(node, "allwinner,sun8i-a33") ||
OF_is_compatible(node, "allwinner,sun8i-h3") ||
OF_is_compatible(node, "allwinner,sun9i-a80") ||
OF_is_compatible(node, "allwinner,sun50i-a64") ||
@@ -118,6 +122,8 @@ sxiccmu_match(struct device *parent, voi
return (OF_is_compatible(node, "allwinner,sun4i-a10-ccu") ||
OF_is_compatible(node, "allwinner,sun7i-a20-ccu") ||
+ OF_is_compatible(node, "allwinner,sun8i-a23-ccu") ||
+ OF_is_compatible(node, "allwinner,sun8i-a33-ccu") ||
OF_is_compatible(node, "allwinner,sun8i-h3-ccu") ||
OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
@@ -150,6 +156,15 @@ sxiccmu_attach(struct device *parent, st
sc->sc_nresets = nitems(sun4i_a10_resets);
sc->sc_get_frequency = sxiccmu_a10_get_frequency;
sc->sc_set_frequency = sxiccmu_a10_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun8i-a23-ccu") ||
+ OF_is_compatible(node, "allwinner,sun8i-a33-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun8i_a23_gates;
+ sc->sc_ngates = nitems(sun8i_a23_gates);
+ sc->sc_resets = sun8i_a23_resets;
+ sc->sc_nresets = nitems(sun8i_a23_resets);
+ sc->sc_get_frequency = sxiccmu_a23_get_frequency;
+ sc->sc_set_frequency = sxiccmu_a23_set_frequency;
} else if (OF_is_compatible(node, "allwinner,sun8i-h3-ccu") ||
OF_is_compatible(node, "allwinner,sun50i-h5-ccu")) {
KASSERT(faa->fa_nreg > 0);
@@ -357,6 +372,32 @@ struct sxiccmu_device sxiccmu_devices[]
.get_frequency = sxiccmu_apbs_get_frequency
},
{
+ .compat = "allwinner,sun8i-a23-ahb1-gates-clk",
+ .get_frequency = sxiccmu_gen_get_frequency,
+ .enable = sxiccmu_gate_enable
+ },
+ {
+ .compat = "allwinner,sun8i-a23-apb0-gates-clk",
+ .get_frequency = sxiccmu_gen_get_frequency,
+ .enable = sxiccmu_gate_enable
+ },
+ {
+ .compat = "allwinner,sun8i-a23-apb1-gates-clk",
+ .get_frequency = sxiccmu_gen_get_frequency,
+ .enable = sxiccmu_gate_enable
+ },
+ {
+ .compat = "allwinner,sun8i-a23-apb2-gates-clk",
+ .get_frequency = sxiccmu_gen_get_frequency,
+ .enable = sxiccmu_gate_enable
+ },
+ {
+ .compat = "allwinner,sun8i-a23-usb-clk",
+ .get_frequency = sxiccmu_gen_get_frequency,
+ .enable = sxiccmu_gate_enable,
+ .reset = sxiccmu_reset
+ },
+ {
.compat = "allwinner,sun8i-h3-apb0-gates-clk",
.get_frequency = sxiccmu_gen_get_frequency,
.enable = sxiccmu_gate_enable
@@ -829,6 +870,50 @@ sxiccmu_a10_get_frequency(struct sxiccmu
#define CCU_AHB2_CLK_CFG (3 << 0)
uint32_t
+sxiccmu_a23_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+ uint32_t parent;
+ uint32_t reg, div;
+
+ switch (idx) {
+ case A23_CLK_LOSC:
+ return clock_get_frequency(sc->sc_node, "losc");
+ case A23_CLK_HOSC:
+ return clock_get_frequency(sc->sc_node, "hosc");
+ case A23_CLK_PLL_PERIPH:
+ /* Not hardcoded, but recommended. */
+ return 600000000;
+ case A23_CLK_APB2:
+ /* XXX Controlled by a MUX. */
+ return 24000000;
+ case A23_CLK_AHB1:
+ reg = SXIREAD4(sc, CCU_AHB1_APB1_CFG_REG);
+ div = CCU_AHB1_CLK_DIV_RATIO(reg);
+ switch (reg & CCU_AHB1_CLK_SRC_SEL) {
+ case CCU_AHB1_CLK_SRC_SEL_LOSC:
+ parent = A23_CLK_LOSC;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_OSC24M:
+ parent = A23_CLK_HOSC;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_AXI:
+ parent = A23_CLK_AXI;
+ break;
+ case CCU_AHB1_CLK_SRC_SEL_PERIPH0:
+ parent = A23_CLK_PLL_PERIPH;
+ div *= CCU_AHB1_PRE_DIV(reg);
+ break;
+ default:
+ return 0;
+ }
+ return sxiccmu_ccu_get_frequency(sc, &parent) / div;
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return 0;
+}
+
+uint32_t
sxiccmu_a64_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
{
uint32_t parent;
@@ -995,6 +1080,28 @@ sxiccmu_a10_set_frequency(struct sxiccmu
bus_space_subregion(sc->sc_iot, sc->sc_ioh,
sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
parent = A10_CLK_PLL_PERIPH;
+ parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
+ return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
+ }
+
+ printf("%s: 0x%08x\n", __func__, idx);
+ return -1;
+}
+
+int
+sxiccmu_a23_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t
freq)
+{
+ struct sxiccmu_clock clock;
+ uint32_t parent, parent_freq;
+
+ switch (idx) {
+ case A23_CLK_MMC0:
+ case A23_CLK_MMC1:
+ case A23_CLK_MMC2:
+ clock.sc_iot = sc->sc_iot;
+ bus_space_subregion(sc->sc_iot, sc->sc_ioh,
+ sc->sc_gates[idx].reg, 4, &clock.sc_ioh);
+ parent = A23_CLK_PLL_PERIPH;
parent_freq = sxiccmu_ccu_get_frequency(sc, &parent);
return sxiccmu_mmc_do_set_frequency(&clock, freq, parent_freq);
}
Index: sys/dev/fdt/sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.11
diff -u -p -u -p -r1.11 sxiccmu_clocks.h
--- sys/dev/fdt/sxiccmu_clocks.h 24 Dec 2017 18:24:06 -0000 1.11
+++ sys/dev/fdt/sxiccmu_clocks.h 26 Dec 2017 07:56:08 -0000
@@ -80,6 +80,54 @@ struct sxiccmu_ccu_bit sun4i_a10_gates[]
[A10_CLK_USB_PHY] = { 0x00cc, 8 },
};
+/* A23/A33 */
+
+#define A23_CLK_PLL_PERIPH 10
+
+#define A23_CLK_AXI 19
+#define A23_CLK_AHB1 20
+#define A23_CLK_APB1 21
+#define A23_CLK_APB2 22
+
+#define A23_CLK_BUS_MMC0 26
+#define A23_CLK_BUS_MMC1 27
+#define A23_CLK_BUS_MMC2 28
+#define A23_CLK_BUS_EHCI 35
+#define A23_CLK_BUS_OHCI 36
+#define A23_CLK_BUS_PIO 48
+#define A23_CLK_BUS_I2C0 51
+#define A23_CLK_BUS_I2C1 52
+#define A23_CLK_BUS_I2C2 53
+#define A23_CLK_BUS_UART0 54
+#define A23_CLK_BUS_UART1 55
+#define A23_CLK_BUS_UART2 56
+#define A23_CLK_BUS_UART3 57
+#define A23_CLK_BUS_UART4 58
+
+#define A23_CLK_MMC0 60
+#define A23_CLK_MMC1 63
+#define A23_CLK_MMC2 66
+
+struct sxiccmu_ccu_bit sun8i_a23_gates[] = {
+ [A23_CLK_BUS_MMC0] = { 0x0060, 8 },
+ [A23_CLK_BUS_MMC1] = { 0x0060, 9 },
+ [A23_CLK_BUS_MMC2] = { 0x0060, 10 },
+ [A23_CLK_BUS_EHCI] = { 0x0060, 26 },
+ [A23_CLK_BUS_OHCI] = { 0x0060, 29 },
+ [A23_CLK_BUS_PIO] = { 0x0068, 5 },
+ [A23_CLK_BUS_I2C0] = { 0x006c, 0, A23_CLK_APB2 },
+ [A23_CLK_BUS_I2C1] = { 0x006c, 1, A23_CLK_APB2 },
+ [A23_CLK_BUS_I2C2] = { 0x006c, 2, A23_CLK_APB2 },
+ [A23_CLK_BUS_UART0] = { 0x006c, 16, A23_CLK_APB2 },
+ [A23_CLK_BUS_UART1] = { 0x006c, 17, A23_CLK_APB2 },
+ [A23_CLK_BUS_UART2] = { 0x006c, 18, A23_CLK_APB2 },
+ [A23_CLK_BUS_UART3] = { 0x006c, 19, A23_CLK_APB2 },
+ [A23_CLK_BUS_UART4] = { 0x006c, 20, A23_CLK_APB2 },
+ [A23_CLK_MMC0] = { 0x0088, 31 },
+ [A23_CLK_MMC1] = { 0x008c, 31 },
+ [A23_CLK_MMC2] = { 0x0090, 31 },
+};
+
/* A64 */
#define A64_CLK_PLL_PERIPH0 11
@@ -307,6 +355,38 @@ struct sxiccmu_ccu_bit sun4i_a10_resets[
[A10_RST_USB_PHY0] = { 0x00cc, 0 },
[A10_RST_USB_PHY1] = { 0x00cc, 1 },
[A10_RST_USB_PHY2] = { 0x00cc, 2 },
+};
+
+/* A23/A33 */
+
+#define A23_RST_USB_PHY0 0
+#define A23_RST_USB_PHY1 1
+
+#define A23_RST_BUS_MMC0 7
+#define A23_RST_BUS_MMC1 8
+#define A23_RST_BUS_MMC2 9
+
+#define A23_RST_BUS_EHCI 16
+#define A23_RST_BUS_OHCI 17
+
+#define A23_RST_BUS_I2C0 32
+#define A23_RST_BUS_I2C1 33
+#define A23_RST_BUS_I2C2 34
+
+#define A23_CLK_HOSC 253
+#define A23_CLK_LOSC 254
+
+struct sxiccmu_ccu_bit sun8i_a23_resets[] = {
+ [A23_RST_USB_PHY0] = { 0x00cc, 0 },
+ [A23_RST_USB_PHY1] = { 0x00cc, 1 },
+ [A23_RST_BUS_MMC0] = { 0x02c0, 8 },
+ [A23_RST_BUS_MMC1] = { 0x02c0, 9 },
+ [A23_RST_BUS_MMC2] = { 0x02c0, 10 },
+ [A23_RST_BUS_EHCI] = { 0x02c0, 26 },
+ [A23_RST_BUS_OHCI] = { 0x02c0, 29 },
+ [A23_RST_BUS_I2C0] = { 0x02d8, 0 },
+ [A23_RST_BUS_I2C1] = { 0x02d8, 1 },
+ [A23_RST_BUS_I2C2] = { 0x02d8, 2 },
};
/* A64 */
Index: sys/dev/fdt/sxipio.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio.c,v
retrieving revision 1.6
diff -u -p -u -p -r1.6 sxipio.c
--- sys/dev/fdt/sxipio.c 23 Dec 2017 12:28:45 -0000 1.6
+++ sys/dev/fdt/sxipio.c 26 Dec 2017 07:56:08 -0000
@@ -134,6 +134,10 @@ struct sxipio_pins sxipio_pins[] = {
sun7i_a20_pins, nitems(sun7i_a20_pins)
},
{
+ "allwinner,sun8i-a33-pinctrl",
+ sun8i_a33_pins, nitems(sun8i_a33_pins)
+ },
+ {
"allwinner,sun8i-h3-pinctrl",
sun8i_h3_pins, nitems(sun8i_h3_pins)
},
Index: sys/dev/fdt/sxipio_pins.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio_pins.h,v
retrieving revision 1.2
diff -u -p -u -p -r1.2 sxipio_pins.h
--- sys/dev/fdt/sxipio_pins.h 23 Dec 2017 12:55:26 -0000 1.2
+++ sys/dev/fdt/sxipio_pins.h 26 Dec 2017 07:56:08 -0000
@@ -3513,6 +3513,555 @@ struct sxipio_pin sun7i_a20_pins[] = {
} },
};
+struct sxipio_pin sun8i_a33_pins[] = {
+ { SXIPIO_PIN(B, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "uart0", 3 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "uart0", 3 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart2", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s0", 2 },
+ { "aif2", 3 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s0", 2 },
+ { "aif2", 3 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s0", 2 },
+ { "aif2", 3 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(B, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s0", 2 },
+ { "aif2", 3 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(C, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "spi0", 3 },
+ } },
+ { SXIPIO_PIN(C, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ } },
+ { SXIPIO_PIN(C, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ } },
+ { SXIPIO_PIN(C, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(C, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "nand0", 2 },
+ { "mmc2", 3 },
+ } },
+ { SXIPIO_PIN(D, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "mmc1", 3 },
+ } },
+ { SXIPIO_PIN(D, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "mmc1", 3 },
+ } },
+ { SXIPIO_PIN(D, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "mmc1", 3 },
+ } },
+ { SXIPIO_PIN(D, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "mmc1", 3 },
+ } },
+ { SXIPIO_PIN(D, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "mmc1", 3 },
+ } },
+ { SXIPIO_PIN(D, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "mmc1", 3 },
+ } },
+ { SXIPIO_PIN(D, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "uart1", 3 },
+ } },
+ { SXIPIO_PIN(D, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "uart1", 3 },
+ } },
+ { SXIPIO_PIN(D, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "uart1", 3 },
+ } },
+ { SXIPIO_PIN(D, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "uart1", 3 },
+ } },
+ { SXIPIO_PIN(D, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ } },
+ { SXIPIO_PIN(D, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ } },
+ { SXIPIO_PIN(D, 18), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 19), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 20), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 21), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 22), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 23), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 24), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 25), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 26), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(D, 27), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "lcd0", 2 },
+ { "lvds0", 3 },
+ } },
+ { SXIPIO_PIN(E, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ } },
+ { SXIPIO_PIN(E, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "i2c2", 3 },
+ } },
+ { SXIPIO_PIN(E, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "csi", 2 },
+ { "i2c2", 3 },
+ } },
+ { SXIPIO_PIN(E, 14), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ } },
+ { SXIPIO_PIN(E, 15), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ } },
+ { SXIPIO_PIN(E, 16), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ } },
+ { SXIPIO_PIN(E, 17), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ } },
+ { SXIPIO_PIN(F, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ } },
+ { SXIPIO_PIN(F, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(F, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "uart0", 3 },
+ } },
+ { SXIPIO_PIN(F, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc0", 2 },
+ { "jtag", 3 },
+ } },
+ { SXIPIO_PIN(G, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "mmc1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 8), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "uart1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 10), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 11), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 12), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(G, 13), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2s1", 2 },
+ { "irq", 4 },
+ } },
+ { SXIPIO_PIN(H, 0), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "pwm0", 2 },
+ } },
+ { SXIPIO_PIN(H, 1), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "pwm1", 2 },
+ } },
+ { SXIPIO_PIN(H, 2), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 },
+ } },
+ { SXIPIO_PIN(H, 3), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c0", 2 },
+ } },
+ { SXIPIO_PIN(H, 4), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c1", 2 },
+ } },
+ { SXIPIO_PIN(H, 5), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "i2c1", 2 },
+ } },
+ { SXIPIO_PIN(H, 6), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "spi0", 2 },
+ { "uart3", 3 },
+ } },
+ { SXIPIO_PIN(H, 7), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "spi0", 2 },
+ { "uart3", 3 },
+ } },
+ { SXIPIO_PIN(H, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "spi0", 2 },
+ { "uart3", 3 },
+ } },
+ { SXIPIO_PIN(H, 9), {
+ { "gpio_in", 0 },
+ { "gpio_out", 1 },
+ { "spi0", 2 },
+ { "uart3", 3 },
+ } },
+};
+
struct sxipio_pin sun8i_h3_pins[] = {
{ SXIPIO_PIN(A, 0), {
{ "gpio_in", 0 },
