The diff below fixes the setjmp implementation on armv7 to save and
restore the required floating-point registers. The existing (but
disabled) code was written for the old FPA FPU. The new VFP FPU
requires us to save a bit more stuff. Fortunately the setjmp buffer
was already big enough so we just have to change te layout a bit and
don't have to have a full flag day. Code that does peek or poke at
the contents of a setjmp buffer will have to be recompiled. But such
code deserves to break.
Unfortunately this doesn't fix the /bin/sh crashes that now occur
regularly on armv7 :(.
ok?
Index: sys/arch/arm/include/setjmp.h
===================================================================
RCS file: /cvs/src/sys/arch/arm/include/setjmp.h,v
retrieving revision 1.4
diff -u -p -r1.4 setjmp.h
--- sys/arch/arm/include/setjmp.h 7 Aug 2016 02:02:57 -0000 1.4
+++ sys/arch/arm/include/setjmp.h 20 Jun 2018 16:00:13 -0000
@@ -11,26 +11,23 @@
* Description of the setjmp buffer
*
* word 0 magic number (dependant on creator)
- * 1 - 3 f4 fp register 4
- * 4 - 6 f5 fp register 5
- * 7 - 9 f6 fp register 6
- * 10 - 12 f7 fp register 7
- * 13 fpsr fp status register
- * 14 r13 register 13 (sp) XOR cookie0
- * 15 r14 register 14 (lr) XOR cookie1
- * 16 r4 register 4
- * 17 r5 register 5
- * 18 r6 register 6
- * 19 r7 register 7
- * 20 r8 register 8
- * 21 r9 register 9
- * 22 r10 register 10 (sl)
- * 23 r11 register 11 (fp)
- * 24 unused unused
- * 25 signal mask (dependant on magic)
- * 26 (con't)
- * 27 (con't)
- * 28 (con't)
+ * 1 fpscr fpscr
+ * 2 - 17 d8 - d15 vfp registers
+ * 18 r13 register 13 (sp) XOR cookie0
+ * 19 r14 register 14 (lr) XOR cookie1
+ * 20 r4 register 4
+ * 21 r5 register 5
+ * 22 r6 register 6
+ * 23 r7 register 7
+ * 24 r8 register 8
+ * 25 r9 register 9
+ * 26 r10 register 10 (sl)
+ * 27 r11 register 11 (fp)
+ * 28 unused unused
+ * 29 signal mask (dependant on magic)
+ * 30 (con't)
+ * 31 (con't)
+ * 32 (con't)
*
* The magic number number identifies the jmp_buf and
* how the buffer was created as well as providing
@@ -56,20 +53,15 @@
/* Valid for all jmp_buf's */
#define _JB_MAGIC 0
-#define _JB_REG_F4 1
-#define _JB_REG_F5 4
-#define _JB_REG_F6 7
-#define _JB_REG_F7 10
-#define _JB_REG_FPSR 13
-#define _JB_REG_R4 16
-#define _JB_REG_R5 17
-#define _JB_REG_R6 18
-#define _JB_REG_R7 19
-#define _JB_REG_R8 20
-#define _JB_REG_R9 21
-#define _JB_REG_R10 22
-#define _JB_REG_R11 23
+#define _JB_REG_R4 20
+#define _JB_REG_R5 21
+#define _JB_REG_R6 22
+#define _JB_REG_R7 23
+#define _JB_REG_R8 24
+#define _JB_REG_R9 25
+#define _JB_REG_R10 26
+#define _JB_REG_R11 27
/* Only valid with the _JB_MAGIC_SETJMP magic */
-#define _JB_SIGMASK 25
+#define _JB_SIGMASK 29
Index: lib/libc/arch/arm/Makefile.inc
===================================================================
RCS file: /cvs/src/lib/libc/arch/arm/Makefile.inc,v
retrieving revision 1.8
diff -u -p -r1.8 Makefile.inc
--- lib/libc/arch/arm/Makefile.inc 28 Feb 2018 11:16:54 -0000 1.8
+++ lib/libc/arch/arm/Makefile.inc 20 Jun 2018 16:00:13 -0000
@@ -5,8 +5,6 @@
CERROR= cerror.S
-CPPFLAGS += -DSOFTFLOAT
-
# Override softfloat implementations of FP mode control functions
.PATH: ${LIBCSRCDIR}/arch/${MACHINE_CPU}/gen
Index: lib/libc/arch/arm/gen/_setjmp.S
===================================================================
RCS file: /cvs/src/lib/libc/arch/arm/gen/_setjmp.S,v
retrieving revision 1.5
diff -u -p -r1.5 _setjmp.S
--- lib/libc/arch/arm/gen/_setjmp.S 7 Aug 2016 02:02:57 -0000 1.5
+++ lib/libc/arch/arm/gen/_setjmp.S 20 Jun 2018 16:00:13 -0000
@@ -69,13 +69,13 @@ ENTRY(_setjmp)
eor r3, lr, r3 /* r3 = lr ^ __jmpxor[1] */
#ifdef SOFTFLOAT
- add r0, r0, #52
+ add r0, r0, #68
#else
+ /* Store fpcsr */
+ vmrs r1, fpscr
+ str r1, [r0], #4
/* Store fp registers */
- sfm f4, 4, [r0], #48
- /* Store fpsr */
- rfs r1
- str r1, [r0], #0x0004
+ vstmia r0!, {d8-d15}
#endif /* SOFTFLOAT */
/* Store integer registers */
stmia r0, {r2-r11}
@@ -98,13 +98,13 @@ ENTRY(_longjmp)
bne botch
#ifdef SOFTFLOAT
- add r0, r0, #52
+ add r0, r0, #68
#else
+ /* Restore fpcsr */
+ ldr r4, [r0], #4
+ vmsr fpscr, r4
/* Restore fp registers */
- lfm f4, 4, [r0], #48
- /* Restore fpsr */
- ldr r4, [r0], #0x0004
- wfs r4
+ vldmia r0!, {d8-d15}
#endif /* SOFTFLOAT */
/* Restore integer registers */
ldmia r0, {r2-r11}
Index: lib/libc/arch/arm/gen/setjmp.S
===================================================================
RCS file: /cvs/src/lib/libc/arch/arm/gen/setjmp.S,v
retrieving revision 1.6
diff -u -p -r1.6 setjmp.S
--- lib/libc/arch/arm/gen/setjmp.S 7 Aug 2016 02:02:57 -0000 1.6
+++ lib/libc/arch/arm/gen/setjmp.S 20 Jun 2018 16:00:13 -0000
@@ -56,7 +56,7 @@ ENTRY(setjmp)
SYSTRAP(sigprocmask)
/* Store signal mask */
- str r0, [r2, #(25 * 4)]
+ str r0, [r2, #(29 * 4)]
ldr r1, .Lsetjmp_magic
str r1, [r2], #4
@@ -69,14 +69,14 @@ ENTRY(setjmp)
eor r3, lr, r3 /* r3 = lr ^ __jmpxor[1] */
#ifdef SOFTFLOAT
- add r2, r2, #52
+ add r2, r2, #68
#else
+ /* Store fpcsr */
+ vmrs r1, fpscr
+ str r1, [r2], #4
/* Store fp registers */
- sfm f4, 4, [r2], #48
- /* Store fpsr */
- rfs r1
- str r1, [r2], #0x0004
-#endif /*SOFTFLOAT*/
+ vstmia r2!, {d8-d15}
+#endif /* SOFTFLOAT */
/* Store integer registers */
stmia r2, {r3-r12}
@@ -101,19 +101,19 @@ ENTRY(longjmp)
/* Fetch signal mask and call sigprocmask */
mov r3, r0 /* r3 = jmpbuf */
mov r2, r1 /* r2 = retvalue */
- ldr r1, [r0, #(25 * 4)]
+ ldr r1, [r0, #(29 * 4)]
mov r0, #0x00000003 /* SIG_SETMASK */
SYSTRAP(sigprocmask)
add r3, r3, #4
#ifdef SOFTFLOAT
- add r3, r3, #52
+ add r3, r3, #68
#else
+ /* Restore fpcsr */
+ ldr r4, [r3], #4
+ vmsr fpscr, r4
/* Restore fp registers */
- lfm f4, 4, [r3], #48
- /* Restore FPSR */
- ldr r4, [r3], #0x0004
- wfs r4
+ vldmia r3!, {d8-d15}
#endif /* SOFTFLOAT */
/* Restore integer registers */
ldmia r3, {r3-r12}
