On Thu, Feb 21, 2019 at 10:50:40AM +0100, Patrick Wildt wrote: > Hi, > > on my i.MX8M machine which features a DWC3 xHCI 1.10 controller I have > seen this error while installing base64.tgz or running fsck: > > umass0: Invalid CSW: sig 0x43425355 should be 0x53425355 > > As it turns out using a USB protocol analyzer, the transfers actually > seem fine, the USB mass storage is not responding nonsense. By further > looking into it I realized that our xhci(4) is told the transfer was > completed, even though the buffer had not been touched. > > Further debugging revealed that the issue occured when a transfer that > spans multiple TRBs loops over the ring. This means one TRB is using > idx 254, the next TRB is the link TRB which does not contain data and > sits at idx 255, and the following data TRB is using idx 0. > > Transfers that comprise of multiple TRBs must have the chain bit set in > all but the last TRB. Now in this case the link TRB which sits in the > middle does not get the chain bit set, and thus processing stops. > > Somewhere I have seen code that always sets the chain bit in the link > TRB, so I'm wondering if we should follow that too. For now I think the > easiest fix for this is to set the chain bit in the link TRB if the > transfer spans multiple TRBs. > > Feedback?
Is this why the #if 0 isochronous transfer code doesn't work?
