Paul Irofti <p...@irofti.net> writes: > Hi, > > Here is an initial diff, adapted from NetBSD, that synchronizes TSC > clocks across cores. > > CPU0 is the reference clock and all others are skewed. During CPU > initialization the clocks synchronize by keeping a registry of each CPU > clock skewness and adapting the TSC read routine accordingly. > > I choose this implementation over what FreeBSD is doing (which is just > copying Linux really), because it is clean and elegant. > > I would love to hear reports from machines that were broken by this. > Mine, which never exhibited the problem in the first place, run just > fine with the following diff. In fact I am writting this message on one > such machine. > > Also constructive comments are more than welcomed! > > Notes: > > - cpu_counter_serializing() could probably have a better name > (tsc _read for example) > - the PAUSE instruction is probably not needed > - acpi(4) suspend and resume bits are left out on purpose, but should > be trivial to add once the current diff settles > > Paul Irofti > > Index: arch/amd64/amd64/cpu.c > =================================================================== > RCS file: /cvs/src/sys/arch/amd64/amd64/cpu.c,v > retrieving revision 1.137 > diff -u -p -u -p -r1.137 cpu.c > --- arch/amd64/amd64/cpu.c 28 May 2019 18:17:01 -0000 1.137 > +++ arch/amd64/amd64/cpu.c 27 Jun 2019 11:55:08 -0000 > @@ -96,6 +96,7 @@ > #include <machine/gdt.h> > #include <machine/pio.h> > #include <machine/vmmvar.h> > +#include <machine/tsc.h> > > #if NLAPIC > 0 > #include <machine/i82489reg.h> > @@ -754,6 +755,10 @@ cpu_init(struct cpu_info *ci) > cr4 = rcr4(); > lcr4(cr4 & ~CR4_PGE); > lcr4(cr4); > + > + /* Synchronize TSC */ > + if (!CPU_IS_PRIMARY(ci)) > + tsc_sync_ap(ci); > #endif > } > > @@ -808,6 +813,7 @@ void > cpu_start_secondary(struct cpu_info *ci) > { > int i; > + u_long s; > > ci->ci_flags |= CPUF_AP; > > @@ -828,8 +834,20 @@ cpu_start_secondary(struct cpu_info *ci) > printf("dropping into debugger; continue from here to resume > boot\n"); > db_enter(); > #endif > + } else { > + /* > + * Synchronize time stamp counters. Invalidate cache and do > + * twice (in tsc_sync_bp) to minimize possible cache effects. > + * Disable interrupts to try and rule out any external > + * interference. > + */ > + s = intr_disable(); > + wbinvd(); > + tsc_sync_bp(ci); > + intr_restore(s); > } > > + > if ((ci->ci_flags & CPUF_IDENTIFIED) == 0) { > atomic_setbits_int(&ci->ci_flags, CPUF_IDENTIFY); > > @@ -852,6 +870,8 @@ void > cpu_boot_secondary(struct cpu_info *ci) > { > int i; > + int64_t drift; > + u_long s; > > atomic_setbits_int(&ci->ci_flags, CPUF_GO); > > @@ -864,6 +884,17 @@ cpu_boot_secondary(struct cpu_info *ci) > printf("dropping into debugger; continue from here to resume > boot\n"); > db_enter(); > #endif > + } else { > + /* Synchronize TSC again, check for drift. */ > + drift = ci->cpu_cc_skew; > + s = intr_disable(); > + wbinvd(); > + tsc_sync_bp(ci); > + intr_restore(s); > + drift -= ci->cpu_cc_skew; > + printf("TSC skew=%lld drift=%lld\n", > + (long long)ci->cpu_cc_skew, (long long)drift); > + tsc_sync_drift(drift); > } > } > > @@ -888,7 +919,13 @@ cpu_hatch(void *v) > panic("%s: already running!?", ci->ci_dev->dv_xname); > #endif > > + /* > + * Synchronize the TSC for the first time. Note that interrupts are > + * off at this point. > + */ > + wbinvd(); > ci->ci_flags |= CPUF_PRESENT; > + tsc_sync_ap(ci); > > lapic_enable(); > lapic_startclock(); > Index: arch/amd64/amd64/tsc.c > =================================================================== > RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v > retrieving revision 1.11 > diff -u -p -u -p -r1.11 tsc.c > --- arch/amd64/amd64/tsc.c 6 Jun 2019 19:43:35 -0000 1.11 > +++ arch/amd64/amd64/tsc.c 27 Jun 2019 11:55:08 -0000 > @@ -1,8 +1,10 @@ > /* $OpenBSD: tsc.c,v 1.11 2019/06/06 19:43:35 kettenis Exp $ */ > /* > + * Copyright (c) 2008 The NetBSD Foundation, Inc. > * Copyright (c) 2016,2017 Reyk Floeter <r...@openbsd.org> > * Copyright (c) 2017 Adam Steen <a...@adamsteen.com.au> > * Copyright (c) 2017 Mike Belopuhov <m...@openbsd.org> > + * Copyright (c) 2019 Paul Irofti <piro...@openbsd.org> > * > * Permission to use, copy, modify, and distribute this software for any > * purpose with or without fee is hereby granted, provided that the above > @@ -20,6 +22,7 @@ > #include <sys/param.h> > #include <sys/systm.h> > #include <sys/timetc.h> > +#include <sys/atomic.h> > > #include <machine/cpu.h> > #include <machine/cpufunc.h> > @@ -33,6 +36,13 @@ int tsc_recalibrate; > uint64_t tsc_frequency; > int tsc_is_invariant; > > +static int64_t tsc_drift_max = 250; /* max cycles */ > +static int64_t tsc_drift_observed; > +static bool tsc_good; > + > +static volatile int64_t tsc_sync_val; > +static volatile struct cpu_info *tsc_sync_cpu; > + > uint tsc_get_timecount(struct timecounter *tc); > > struct timecounter tsc_timecounter = { > @@ -172,10 +182,8 @@ calibrate_tsc_freq(void) > return; > tsc_frequency = freq; > tsc_timecounter.tc_frequency = freq; > -#ifndef MULTIPROCESSOR > if (tsc_is_invariant) > tsc_timecounter.tc_quality = 2000; > -#endif > } > > void > @@ -208,12 +216,12 @@ tsc_timecounter_init(struct cpu_info *ci > tsc_frequency = tsc_freq_cpuid(ci); > tsc_is_invariant = 1; > > + tsc_good = (rdmsr(MSR_TSC) != 0 || rdmsr(MSR_TSC) != 0); > + > /* Newer CPUs don't require recalibration */ > if (tsc_frequency > 0) { > tsc_timecounter.tc_frequency = tsc_frequency; > -#ifndef MULTIPROCESSOR > tsc_timecounter.tc_quality = 2000; > -#endif > } else { > tsc_recalibrate = 1; > tsc_frequency = cpufreq; > @@ -221,5 +229,116 @@ tsc_timecounter_init(struct cpu_info *ci > calibrate_tsc_freq(); > } > > + if (tsc_drift_observed > tsc_drift_max) { > + printf("ERROR: %lld cycle TSC drift observed\n", > + (long long)tsc_drift_observed); > + tsc_timecounter.tc_quality = -100; > + tsc_is_invariant = 0; > + } > + > tc_init(&tsc_timecounter); > +} > + > +static uint64_t > +cpu_counter_serializing(struct cpu_info *ci) > +{ > + if (tsc_good) > + return rdmsr(MSR_TSC); > + else > + return (rdtsc() + ci->cpu_cc_skew); > +} > + > +/* > + * Record drift (in clock cycles). Called during AP startup. > + */ > +void > +tsc_sync_drift(int64_t drift) > +{ > + > + if (drift < 0) > + drift = -drift; > + if (drift > tsc_drift_observed) > + tsc_drift_observed = drift; > +} > + > +/* > + * Called during startup of APs, by the boot processor. Interrupts > + * are disabled on entry. > + */ > +static void > +tsc_read_bp(struct cpu_info *ci, uint64_t *bptscp, uint64_t *aptscp) > +{ > + uint64_t bptsc; > + > + if (atomic_swap_ptr(&tsc_sync_cpu, ci) != NULL) { > + panic("tsc_sync_bp: 1"); > + } > + > + /* Flag it and read our TSC. */ > + atomic_setbits_int(&ci->ci_flags, CPUF_SYNCTSC); > + bptsc = cpu_counter_serializing(ci) >> 1; > + > + /* Wait for remote to complete, and read ours again. */ > + while ((ci->ci_flags & CPUF_SYNCTSC) != 0) { > + membar_consumer(); > + } > + bptsc += (cpu_counter_serializing(ci) >> 1); > + > + /* Wait for the results to come in. */ > + while (tsc_sync_cpu == ci) { > + pause(); > + } > + if (tsc_sync_cpu != NULL) { > + panic("tsc_sync_bp: 2"); > + } > + > + *bptscp = bptsc; > + *aptscp = tsc_sync_val; > +} > + > +void > +tsc_sync_bp(struct cpu_info *ci) > +{ > + uint64_t bptsc, aptsc; > + > + tsc_read_bp(ci, &bptsc, &aptsc); /* discarded - cache effects */ > + tsc_read_bp(ci, &bptsc, &aptsc); > + > + /* Compute final value to adjust for skew. */ > + ci->cpu_cc_skew = bptsc - aptsc; > +} > + > +/* > + * Called during startup of AP, by the AP itself. Interrupts are > + * disabled on entry. > + */ > +static void > +tsc_post_ap(struct cpu_info *ci) > +{ > + uint64_t tsc; > + > + /* Wait for go-ahead from primary. */ > + while ((ci->ci_flags & CPUF_SYNCTSC) == 0) { > + membar_consumer(); > + } > + tsc = (cpu_counter_serializing(ci) >> 1); > + > + /* Instruct primary to read its counter. */ > + atomic_clearbits_int(&ci->ci_flags, CPUF_SYNCTSC); > + tsc += (cpu_counter_serializing(ci) >> 1); > + > + /* Post result. Ensure the whole value goes out atomically. */ > + (void)atomic_swap_64(&tsc_sync_val, tsc); > + > + if (atomic_swap_ptr(&tsc_sync_cpu, NULL) != ci) { > + panic("tsc_sync_ap"); > + } > +} > + > +void > +tsc_sync_ap(struct cpu_info *ci) > +{ > + > + tsc_post_ap(ci); > + tsc_post_ap(ci); > } > Index: arch/amd64/include/cpu.h > =================================================================== > RCS file: /cvs/src/sys/arch/amd64/include/cpu.h,v > retrieving revision 1.131 > diff -u -p -u -p -r1.131 cpu.h > --- arch/amd64/include/cpu.h 17 May 2019 19:07:16 -0000 1.131 > +++ arch/amd64/include/cpu.h 27 Jun 2019 11:55:08 -0000 > @@ -206,6 +206,8 @@ struct cpu_info { > union vmm_cpu_cap ci_vmm_cap; > paddr_t ci_vmxon_region_pa; > struct vmxon_region *ci_vmxon_region; > + > + int64_t cpu_cc_skew; /* counter skew vs cpu0 */ > }; > > #define CPUF_BSP 0x0001 /* CPU is the original BSP */ > @@ -221,6 +223,7 @@ struct cpu_info { > #define CPUF_INVAR_TSC 0x0100 /* CPU has invariant TSC */ > #define CPUF_USERXSTATE 0x0200 /* CPU has curproc's xsave > state */ > > +#define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */ > #define CPUF_PRESENT 0x1000 /* CPU is present */ > #define CPUF_RUNNING 0x2000 /* CPU is running */ > #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ > Index: arch/amd64/include/cpufunc.h > =================================================================== > RCS file: /cvs/src/sys/arch/amd64/include/cpufunc.h,v > retrieving revision 1.33 > diff -u -p -u -p -r1.33 cpufunc.h > --- arch/amd64/include/cpufunc.h 26 Mar 2019 19:32:46 -0000 1.33 > +++ arch/amd64/include/cpufunc.h 27 Jun 2019 11:55:08 -0000 > @@ -282,6 +282,11 @@ mfence(void) > __asm volatile("mfence" : : : "memory"); > } > > +static __inline void > +pause(void) > +{ > + __asm volatile("pause" : : : "memory"); > +} > static __inline u_int64_t > rdtsc(void) > { > Index: arch/amd64/include/tsc.h > =================================================================== > RCS file: arch/amd64/include/tsc.h > diff -N arch/amd64/include/tsc.h > --- /dev/null 1 Jan 1970 00:00:00 -0000 > +++ arch/amd64/include/tsc.h 27 Jun 2019 11:55:08 -0000 > @@ -0,0 +1,25 @@ > +/* $OpenBSD$ */ > +/* > + * Copyright (c) 2019 Paul Irofti <piro...@openbsd.org> > + * > + * Permission to use, copy, modify, and/or distribute this software for any > + * purpose with or without fee is hereby granted, provided that the above > + * copyright notice and this permission notice appear in all copies. > + * > + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES > + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR > + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES > + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN > + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF > + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. > + */ > + > +#ifndef _MACHINE_TSC_H_ > +#define _MACHINE_TSC_H_ > + > +void tsc_sync_drift(int64_t); > +void tsc_sync_bp(struct cpu_info *); > +void tsc_sync_ap(struct cpu_info *); > + > +#endif /* !_MACHINE_TSC_H_ */
This doesn't seem to help with my thinkpad e485. I have still lot of key repeats. OpenBSD 6.5-current (GENERIC.MP) #9: Fri Jun 28 07:41:58 EEST 2019 t...@asteroid.bittivirhe.fi:/usr/src/sys/arch/amd64/compile/GENERIC.MP real mem = 8172609536 (7794MB) avail mem = 7912329216 (7545MB) mpath0 at root scsibus0 at mpath0: 256 targets mainbus0 at root bios0 at mainbus0: SMBIOS rev. 3.1 @ 0x98707000 (59 entries) bios0: vendor LENOVO version "R0UET66W (1.46 )" date 10/26/2018 bios0: LENOVO 20KUCTO1WW acpi0 at bios0: ACPI 5.0 acpi0: sleep states S0 S3 S4 S5 acpi0: tables DSDT FACP SSDT SSDT CRAT CDIT SSDT TPM2 UEFI MSDM BATB HPET APIC MCFG SBST VFCT IVRS FPDT SSDT SSDT SSDT BGRT UEFI SSDT acpi0: wakeup devices GPP0(S3) GPP1(S3) GPP2(S3) GPP3(S3) GPP4(S3) GPP5(S3) GPP6(S3) GP17(S3) XHC0(S3) XHC1(S3) GP18(S3) LID_(S3) SLPB(S3) acpitimer0 at acpi0: 3579545 Hz, 32 bits acpihpet0 at acpi0: 14318180 Hz acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat cpu0 at mainbus0: apid 0 (boot processor) cpu0: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.60 MHz, 17-11-00 cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu0: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu0: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu0: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu0: smt 0, core 0, package 0 mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges cpu0: apic clock running at 24MHz cpu0: mwait min=64, max=64, C-substates=1.1, IBE cpu1 at mainbus0: apid 1 (application processor) cpu1: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu1: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu1: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu1: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu1: smt 1, core 0, package 0 cpu2 at mainbus0: apid 2 (application processor) cpu2: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu2: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu2: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu2: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu2: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu2: smt 0, core 1, package 0 cpu3 at mainbus0: apid 3 (application processor) cpu3: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu3: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu3: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu3: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu3: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu3: smt 1, core 1, package 0 cpu4 at mainbus0: apid 4 (application processor) cpu4: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu4: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu4: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu4: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu4: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu4: smt 0, core 2, package 0 cpu5 at mainbus0: apid 5 (application processor) cpu5: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu5: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu5: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu5: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu5: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu5: smt 1, core 2, package 0 cpu6 at mainbus0: apid 6 (application processor) cpu6: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu6: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu6: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu6: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu6: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu6: smt 0, core 3, package 0 cpu7 at mainbus0: apid 7 (application processor) cpu7: AMD Ryzen 5 2500U with Radeon Vega Mobile Gfx, 1996.23 MHz, 17-11-00 cpu7: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,MMX,FXSR,SSE,SSE2,HTT,SSE3,PCLMUL,MWAIT,SSSE3,FMA3,CX16,SSE4.1,SSE4.2,MOVBE,POPCNT,AES,XSAVE,AVX,F16C,RDRAND,NXE,MMXX,FFXSR,PAGE1GB,RDTSCP,LONG,LAHF,CMPLEG,SVM,EAPICSP,AMCR8,ABM,SSE4A,MASSE,3DNOWP,OSVW,SKINIT,TCE,TOPEXT,CPCTR,DBKP,PCTRL3,MWAITX,ITSC,FSGSBASE,BMI1,AVX2,SMEP,BMI2,RDSEED,ADX,SMAP,CLFLUSHOPT,SHA,IBPB,XSAVEOPT,XSAVEC,XGETBV1,XSAVES cpu7: 64KB 64b/line 4-way I-cache, 32KB 64b/line 8-way D-cache, 512KB 64b/line 8-way L2 cache, 4MB 64b/line 16-way L3 cache cpu7: ITLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu7: DTLB 64 4KB entries fully associative, 64 4MB entries fully associative cpu7: smt 1, core 3, package 0 ioapic0 at mainbus0: apid 32 pa 0xfec00000, version 21, 24 pins, can't remap ioapic1 at mainbus0: apid 33 pa 0xfec01000, version 21, 32 pins, can't remap acpimcfg0 at acpi0 acpimcfg0: addr 0xf8000000, bus 0-63 acpiprt0 at acpi0: bus 0 (PCI0) acpiprt1 at acpi0: bus 1 (GPP0) acpiprt2 at acpi0: bus 2 (GPP1) acpiprt3 at acpi0: bus 3 (GPP2) acpiprt4 at acpi0: bus -1 (GPP3) acpiprt5 at acpi0: bus -1 (GPP4) acpiprt6 at acpi0: bus 4 (GPP5) acpiprt7 at acpi0: bus -1 (GPP6) acpiprt8 at acpi0: bus 5 (GP17) acpiprt9 at acpi0: bus 6 (GP18) acpiec0 at acpi0 acpicpu0 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu1 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu2 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu3 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu4 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu5 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu6 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpicpu7 at acpi0: C2(0@400 io@0x414), C1(0@1 mwait), PSS acpipwrres0 at acpi0: P0ST, resource for SATA acpipwrres1 at acpi0: P3ST, resource for SATA acpibtn0 at acpi0: PWRB acpipci0 at acpi0 PCI0: 0x00000010 0x00000011 0x00000000 acpicmos0 at acpi0 acpibat0 at acpi0: BAT0 model "01AV445" serial 2591 type LiP oem "LGC" acpiac0 at acpi0: AC unit online acpithinkpad0 at acpi0 "SMB0001" at acpi0 not configured acpibtn1 at acpi0: LID_ acpibtn2 at acpi0: SLPB "PNP0C14" at acpi0 not configured "PNP0C14" at acpi0 not configured "PNP0C14" at acpi0 not configured "STM7304" at acpi0 not configured "USBC000" at acpi0 not configured acpivideo0 at acpi0: VGA_ cpu0: 1996 MHz: speeds: 2000 1700 1600 MHz pci0 at mainbus0 bus 0 pchb0 at pci0 dev 0 function 0 "AMD AMD64 17h/1xh Root Complex" rev 0x00 "AMD AMD64 17h/1xh IOMMU" rev 0x00 at pci0 dev 0 function 2 not configured pchb1 at pci0 dev 1 function 0 "AMD AMD64 17h PCIE" rev 0x00 ppb0 at pci0 dev 1 function 1 "AMD AMD64 17h/1xh PCIE" rev 0x00: msi pci1 at ppb0 bus 1 nvme0 at pci1 dev 0 function 0 vendor "Lenovo", unknown product 0x0003 rev 0x00: msix, NVMe 1.2 nvme0: LENSE20256GMSP34MEAT2TA, firmware 2.6.8341, serial 1227066205564 scsibus1 at nvme0: 1 targets sd0 at scsibus1 targ 0 lun 0: <NVMe, LENSE20256GMSP34, 2.6.> SCSI4 0/direct fixed sd0: 244198MB, 512 bytes/sector, 500118192 sectors ppb1 at pci0 dev 1 function 2 "AMD AMD64 17h/1xh PCIE" rev 0x00: msi pci2 at ppb1 bus 2 re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x10: RTL8168GU/8111GU (0x5080), msi, address e8:6a:64:33:83:cc rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0 ppb2 at pci0 dev 1 function 3 "AMD AMD64 17h/1xh PCIE" rev 0x00: msi pci3 at ppb2 bus 3 sdhc0 at pci3 dev 0 function 0 "O2 Micro 0Z8621 SD/MMC" rev 0x01: apic 33 int 8 sdhc0: SDHC 4.0, 50 MHz base clock sdmmc0 at sdhc0: 4-bit, sd high-speed, mmc high-speed, dma ppb3 at pci0 dev 1 function 6 "AMD AMD64 17h/1xh PCIE" rev 0x00: msi pci4 at ppb3 bus 4 iwm0 at pci4 dev 0 function 0 "Intel Dual Band Wireless-AC 8265" rev 0x78, msi pchb2 at pci0 dev 8 function 0 "AMD AMD64 17h PCIE" rev 0x00 ppb4 at pci0 dev 8 function 1 "AMD AMD64 17h/1xh PCIE" rev 0x00 pci5 at ppb4 bus 5 amdgpu0 at pci5 dev 0 function 0 "ATI Radeon Vega" rev 0xc4 drm0 at amdgpu0 amdgpu0: msi azalia0 at pci5 dev 0 function 1 "ATI Radeon Vega HD Audio" rev 0x00: msi azalia0: no supported codecs ccp0 at pci5 dev 0 function 2 "AMD AMD64 17h/1xh Crypto" rev 0x00 xhci0 at pci5 dev 0 function 3 "AMD AMD64 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10 usb0 at xhci0: USB revision 3.0 uhub0 at usb0 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00 addr 1 xhci1 at pci5 dev 0 function 4 "AMD AMD64 17h/1xh xHCI" rev 0x00: msi, xHCI 1.10 usb1 at xhci1: USB revision 3.0 uhub1 at usb1 configuration 1 interface 0 "AMD xHCI root hub" rev 3.00/1.00 addr 1 azalia1 at pci5 dev 0 function 6 "AMD AMD64 17h/1xh HD Audio" rev 0x00: apic 33 int 30 azalia1: codecs: Conexant/0x5111 audio0 at azalia1 ppb5 at pci0 dev 8 function 2 "AMD AMD64 17h/1xh PCIE" rev 0x00 pci6 at ppb5 bus 6 ahci0 at pci6 dev 0 function 0 "AMD FCH AHCI" rev 0x61: msi, AHCI 1.3.1 ahci0: port 0: 6.0Gb/s scsibus2 at ahci0: 32 targets sd1 at scsibus2 targ 0 lun 0: <ATA, Samsung SSD 850, EXM0> SCSI3 0/direct fixed naa.50025388400c34c6 sd1: 488386MB, 512 bytes/sector, 1000215216 sectors, thin "AMD FCH SMBus" rev 0x61 at pci0 dev 20 function 0 not configured pcib0 at pci0 dev 20 function 3 "AMD FCH LPC" rev 0x51 pchb3 at pci0 dev 24 function 0 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb4 at pci0 dev 24 function 1 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb5 at pci0 dev 24 function 2 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb6 at pci0 dev 24 function 3 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb7 at pci0 dev 24 function 4 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb8 at pci0 dev 24 function 5 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb9 at pci0 dev 24 function 6 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 pchb10 at pci0 dev 24 function 7 "AMD AMD64 17h/1xh Data Fabric" rev 0x00 isa0 at pcib0 isadma0 at isa0 pckbc0 at isa0 port 0x60/5 irq 1 irq 12 pckbd0 at pckbc0 (kbd slot) wskbd0 at pckbd0: console keyboard pms0 at pckbc0 (aux slot) wsmouse0 at pms0 mux 0 wsmouse1 at pms0 mux 0 pms0: Synaptics clickpad, firmware 8.16, 0x1e2b1 0x940300 pcppi0 at isa0 port 0x61 spkr0 at pcppi0 vmm0 at mainbus0: SVM/RVI efifb at mainbus0 not configured uhidev0 at uhub0 port 3 configuration 1 interface 0 "Microsoft Microsoft Notebook Optical Mouse with Tilt Wheel" rev 2.00/1.20 addr 2 uhidev0: iclass 3/1, 24 report ids ums0 at uhidev0 reportid 17: 3 buttons, Z dir wsmouse2 at ums0 mux 0 uhid0 at uhidev0 reportid 18: input=0, output=0, feature=1 uhid1 at uhidev0 reportid 19: input=1, output=0, feature=0 uhid2 at uhidev0 reportid 23: input=0, output=0, feature=1 uhid3 at uhidev0 reportid 24: input=0, output=0, feature=1 vscsi0 at root scsibus3 at vscsi0: 256 targets softraid0 at root scsibus4 at softraid0: 256 targets sd2 at scsibus4 targ 1 lun 0: <OPENBSD, SR CRYPTO, 006> SCSI2 0/direct fixed sd2: 227678MB, 512 bytes/sector, 466284711 sectors root on sd2a (88532b67c09ce3ee.a) swap on sd2b dump on sd2b TSC skew=-6129185140 drift=170 TSC skew=-6129184900 drift=-10 TSC skew=-6129184890 drift=-20 TSC skew=-6129184910 drift=30 TSC skew=-6129184910 drift=10 TSC skew=-6129184900 drift=20 TSC skew=-6129184910 drift=30 iwm0: hw rev 0x230, fw ver 22.361476.0, address 68:ec:c5:ad:9a:cb initializing kernel modesetting (RAVEN 0x1002:0x15DD 0x17AA:0x506F 0xC4). amdgpu0: 1920x1080, 32bpp wsdisplay0 at amdgpu0 mux 1: console (std, vt100 emulation), using wskbd0 wsdisplay0: screen 1-5 added (std, vt100 emulation)