Don't limit clflush to Intel processors. This change will result in pmap_flush_cache() on AMD processors changing from wbinvd to a clflush loop with mfence.
agp_flush_cache_range() uses pmap_flush_cache() but has no callers agp_flush_cache() uses wbinvd pmap_flush_cache() is used by drm_clflush_* which is used by ttm (radeondrm and amdgpu) and inteldrm. Index: amd64/amd64/identcpu.c =================================================================== RCS file: /cvs/src/sys/arch/amd64/amd64/identcpu.c,v retrieving revision 1.114 diff -u -p -r1.114 identcpu.c --- amd64/amd64/identcpu.c 17 Mar 2020 03:09:04 -0000 1.114 +++ amd64/amd64/identcpu.c 18 May 2020 04:26:20 -0000 @@ -716,8 +716,8 @@ identifycpu(struct cpu_info *ci) if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) replacesmap(); } -#ifndef SMALL_KERNEL - if (!strncmp(mycpu_model, "Intel", 5)) { + + if (ci->ci_feature_flags & CPUID_CFLUSH) { u_int32_t cflushsz; CPUID(0x01, dummy, cflushsz, dummy, dummy); @@ -725,6 +725,7 @@ identifycpu(struct cpu_info *ci) ci->ci_cflushsz = ((cflushsz >> 8) & 0xff) * 8; } +#ifndef SMALL_KERNEL if (CPU_IS_PRIMARY(ci) && (ci->ci_feature_tpmflags & TPM_SENSOR)) { strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, sizeof(ci->ci_sensordev.xname)); Index: i386/i386/machdep.c =================================================================== RCS file: /cvs/src/sys/arch/i386/i386/machdep.c,v retrieving revision 1.633 diff -u -p -r1.633 machdep.c --- i386/i386/machdep.c 16 May 2020 14:44:44 -0000 1.633 +++ i386/i386/machdep.c 18 May 2020 04:25:07 -0000 @@ -1847,6 +1847,17 @@ identifycpu(struct cpu_info *ci) } } + if (ci->ci_feature_flags & CPUID_CFLUSH) { + u_int regs[4]; + + /* to get the cacheline size you must do cpuid + * with eax 0x01 + */ + + cpuid(0x01, regs); + ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; + } + if (vendor == CPUVENDOR_INTEL) { u_int regs[4]; /* @@ -1859,15 +1870,6 @@ identifycpu(struct cpu_info *ci) */ if (ci->ci_family == 6 && ci->ci_model < 15) ci->ci_feature_flags &= ~CPUID_PAT; - - if (ci->ci_feature_flags & CPUID_CFLUSH) { - /* to get the cacheline size you must do cpuid - * with eax 0x01 - */ - - cpuid(0x01, regs); - ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; - } if (cpuid_level >= 0x1) { cpuid(0x80000000, regs);