There are some free slots, so we can just save it directly after the
FPU registers.
This is needed to fix the lib/libc/setjmp-fpu regress on arm64. But
it isn't enough. Because the hardware doesn't implement the
floating-point exception trap control bits, checking those bits can't
work on arm64 (and armv7). So the 2nd part of this diff sprinkles
some #if/#endif to skip the parts that check those bits.
ok?
Index: lib/libc/arch/aarch64/gen/_setjmp.S
===================================================================
RCS file: /cvs/src/lib/libc/arch/aarch64/gen/_setjmp.S,v
retrieving revision 1.3
diff -u -p -r1.3 _setjmp.S
--- lib/libc/arch/aarch64/gen/_setjmp.S 1 Oct 2018 22:49:50 -0000 1.3
+++ lib/libc/arch/aarch64/gen/_setjmp.S 18 Oct 2020 19:22:40 -0000
@@ -53,7 +53,9 @@ ENTRY(_setjmp)
stp d8, d9, [x0], #16
stp d10, d11, [x0], #16
stp d12, d13, [x0], #16
- stp d14, d15, [x0]
+ stp d14, d15, [x0], #16
+ mrs x1, fpcr
+ str x1, [x0]
#endif
/* Return value */
@@ -92,7 +94,9 @@ ENTRY(_longjmp)
ldp d8, d9, [x0], #16
ldp d10, d11, [x0], #16
ldp d12, d13, [x0], #16
- ldp d14, d15, [x0]
+ ldp d14, d15, [x0], #16
+ ldr x2, [x0]
+ msr fpcr, x2
#endif
/* Load the return value */
Index: lib/libc/arch/aarch64/gen/setjmp.S
===================================================================
RCS file: /cvs/src/lib/libc/arch/aarch64/gen/setjmp.S,v
retrieving revision 1.3
diff -u -p -r1.3 setjmp.S
--- lib/libc/arch/aarch64/gen/setjmp.S 1 Oct 2018 22:49:50 -0000 1.3
+++ lib/libc/arch/aarch64/gen/setjmp.S 18 Oct 2020 19:22:40 -0000
@@ -61,7 +61,9 @@ ENTRY(setjmp)
stp d8, d9, [x0], #16
stp d10, d11, [x0], #16
stp d12, d13, [x0], #16
- stp d14, d15, [x0]
+ stp d14, d15, [x0], #16
+ mrs x1, fpcr
+ str x1, [x0]
/* Return value */
mov x0, #0
@@ -108,7 +110,9 @@ ENTRY(longjmp)
ldp d8, d9, [x0], #16
ldp d10, d11, [x0], #16
ldp d12, d13, [x0], #16
- ldp d14, d15, [x0]
+ ldp d14, d15, [x0], #16
+ ldr x1, [x0]
+ msr fpcr, x1
/* Load the return value */
cmp w3, #0
Index: regress/lib/libc/setjmp-fpu/fpu.c
===================================================================
RCS file: /cvs/src/regress/lib/libc/setjmp-fpu/fpu.c,v
retrieving revision 1.1
diff -u -p -r1.1 fpu.c
--- regress/lib/libc/setjmp-fpu/fpu.c 16 Jan 2020 13:04:02 -0000 1.1
+++ regress/lib/libc/setjmp-fpu/fpu.c 18 Oct 2020 19:34:28 -0000
@@ -34,10 +34,12 @@ main(int argc, char *argv[])
rv = fegetround();
if (rv != FE_UPWARD)
errx(1, "fegetround returned %d, not FE_UPWARD", rv);
+#if !defined(__arm__) && !defined(__aarch64__)
rv = fegetexcept();
if (rv != FE_DIVBYZERO)
errx(1, "fegetexcept returned %d, not FE_DIVBYZERO",
rv);
+#endif
/* Verify that the FPU exception flags weren't clobbered. */
flag = 0;
Index: regress/lib/libc/setjmp-fpu/setjmp-fpu.c
===================================================================
RCS file: /cvs/src/regress/lib/libc/setjmp-fpu/setjmp-fpu.c,v
retrieving revision 1.5
diff -u -p -r1.5 setjmp-fpu.c
--- regress/lib/libc/setjmp-fpu/setjmp-fpu.c 16 Jan 2020 13:04:02 -0000
1.5
+++ regress/lib/libc/setjmp-fpu/setjmp-fpu.c 18 Oct 2020 19:34:28 -0000
@@ -42,10 +42,12 @@ TEST_SETJMP(void)
rv = fegetround();
if (rv != FE_UPWARD)
errx(1, "fegetround returned %d, not FE_UPWARD", rv);
+#if !defined(__arm__) && !defined(__aarch64__)
rv = fegetexcept();
if (rv != FE_DIVBYZERO)
errx(1, "fegetexcept returned %d, not FE_DIVBYZERO",
rv);
+#endif
/* Verify that the FPU exception flags weren't clobbered. */
flag = 0;
