Hi,
Sorry for the delay. I am running the latest snapshot:
kern.version=OpenBSD 6.9-beta (GENERIC.MP) #331: Thu Feb 11 20:28:45 MST 2021
dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
which seems to have the latest updates. However I still do not see battery
levels for my M570. Full dmesg below. Please let me know if I can test anything.
Regards,
Anindya
OpenBSD 6.9-beta (GENERIC.MP) #331: Thu Feb 11 20:28:45 MST 2021
dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 34201006080 (32616MB)
avail mem = 33149145088 (31613MB)
random: good seed from bootblocks
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0: SMBIOS rev. 3.0 @ 0xe0000 (94 entries)
bios0: vendor Dell Inc. version "1.5.6" date 12/07/2016
bios0: Dell Inc. OptiPlex 7040
acpi0 at bios0: ACPI 5.0
acpi0: sleep states S0 S3 S4 S5
acpi0: tables DSDT FACP APIC FPDT FIDT MCFG HPET SSDT SSDT UEFI LPIT SSDT SSDT
SSDT SSDT DBGP DBG2 SSDT SSDT MSDM SLIC DMAR TPM2 ASF! BGRT
acpi0: wakeup devices PEG0(S4) PEGP(S4) PEG1(S4) PEGP(S4) PEG2(S4) PEGP(S4)
PS2K(S3) PS2M(S3) RP09(S4) PXSX(S4) RP10(S4) PXSX(S4) RP11(S4) PXSX(S4)
RP12(S4) PXSX(S4) [...]
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3393.29 MHz, 06-5e-03
cpu0:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu0: 256KB 64b/line 8-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 10 var ranges, 88 fixed ranges
cpu0: apic clock running at 24MHz
cpu0: mwait min=64, max=64, C-substates=0.2.1.2.4.1, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.11 MHz, 06-5e-03
cpu1:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu1: 256KB 64b/line 8-way L2 cache
cpu1: smt 0, core 1, package 0
cpu2 at mainbus0: apid 4 (application processor)
cpu2: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.11 MHz, 06-5e-03
cpu2:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu2: 256KB 64b/line 8-way L2 cache
cpu2: smt 0, core 2, package 0
cpu3 at mainbus0: apid 6 (application processor)
cpu3: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.11 MHz, 06-5e-03
cpu3:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu3: 256KB 64b/line 8-way L2 cache
cpu3: smt 0, core 3, package 0
cpu4 at mainbus0: apid 1 (application processor)
cpu4: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.10 MHz, 06-5e-03
cpu4:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu4: 256KB 64b/line 8-way L2 cache
cpu4: smt 1, core 0, package 0
cpu5 at mainbus0: apid 3 (application processor)
cpu5: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.10 MHz, 06-5e-03
cpu5:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu5: 256KB 64b/line 8-way L2 cache
cpu5: smt 1, core 1, package 0
cpu6 at mainbus0: apid 5 (application processor)
cpu6: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.10 MHz, 06-5e-03
cpu6:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu6: 256KB 64b/line 8-way L2 cache
cpu6: smt 1, core 2, package 0
cpu7 at mainbus0: apid 7 (application processor)
cpu7: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz, 3392.10 MHz, 06-5e-03
cpu7:
FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,SGX,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,MPX,RDSEED,ADX,SMAP,CLFLUSHOPT,PT,SRBDS_CTRL,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN
cpu7: 256KB 64b/line 8-way L2 cache
cpu7: smt 1, core 3, package 0
ioapic0 at mainbus0: apid 2 pa 0xfec00000, version 20, 120 pins
acpimcfg0 at acpi0
acpimcfg0: addr 0xf8000000, bus 0-63
acpihpet0 at acpi0: 23999999 Hz
acpiprt0 at acpi0: bus 0 (PCI0)
acpiprt1 at acpi0: bus 1 (PEG0)
acpiprt2 at acpi0: bus -1 (PEG1)
acpiprt3 at acpi0: bus -1 (PEG2)
acpiprt4 at acpi0: bus -1 (RP09)
acpiprt5 at acpi0: bus -1 (RP10)
acpiprt6 at acpi0: bus -1 (RP11)
acpiprt7 at acpi0: bus -1 (RP12)
acpiprt8 at acpi0: bus -1 (RP13)
acpiprt9 at acpi0: bus -1 (RP01)
acpiprt10 at acpi0: bus -1 (RP02)
acpiprt11 at acpi0: bus -1 (RP03)
acpiprt12 at acpi0: bus -1 (RP04)
acpiprt13 at acpi0: bus -1 (RP05)
acpiprt14 at acpi0: bus -1 (RP06)
acpiprt15 at acpi0: bus -1 (RP07)
acpiprt16 at acpi0: bus -1 (RP08)
acpiprt17 at acpi0: bus -1 (RP17)
acpiprt18 at acpi0: bus -1 (RP18)
acpiprt19 at acpi0: bus -1 (RP19)
acpiprt20 at acpi0: bus -1 (RP20)
acpiprt21 at acpi0: bus -1 (RP14)
acpiprt22 at acpi0: bus -1 (RP15)
acpiprt23 at acpi0: bus -1 (RP16)
acpiec0 at acpi0: not present
acpipci0 at acpi0 PCI0: 0x00000004 0x00000011 0x00000001
acpicmos0 at acpi0
acpibtn0 at acpi0: SLPB
"INT33A1" at acpi0 not configured
acpibtn1 at acpi0: PWRB
"MSFT0101" at acpi0 not configured
"PNP0C14" at acpi0 not configured
"PNP0C0B" at acpi0 not configured
"PNP0C0B" at acpi0 not configured
"PNP0C0B" at acpi0 not configured
"PNP0C0B" at acpi0 not configured
"PNP0C0B" at acpi0 not configured
acpicpu0 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu1 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu2 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu3 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu4 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu5 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu6 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpicpu7 at acpi0: C3(200@256 mwait.1@0x40), C2(200@151 mwait.1@0x33),
C1(1000@1 mwait.1), PSS
acpipwrres0 at acpi0: PG00, resource for PEG0
acpipwrres1 at acpi0: PG01, resource for PEG1
acpipwrres2 at acpi0: PG02, resource for PEG2
acpipwrres3 at acpi0: WRST
acpipwrres4 at acpi0: WRST
acpipwrres5 at acpi0: WRST
acpipwrres6 at acpi0: WRST
acpipwrres7 at acpi0: WRST
acpipwrres8 at acpi0: WRST
acpipwrres9 at acpi0: WRST
acpipwrres10 at acpi0: WRST
acpipwrres11 at acpi0: WRST
acpipwrres12 at acpi0: WRST
acpipwrres13 at acpi0: WRST
acpipwrres14 at acpi0: WRST
acpipwrres15 at acpi0: WRST
acpipwrres16 at acpi0: WRST
acpipwrres17 at acpi0: WRST
acpipwrres18 at acpi0: WRST
acpipwrres19 at acpi0: WRST
acpipwrres20 at acpi0: WRST
acpipwrres21 at acpi0: WRST
acpipwrres22 at acpi0: WRST
acpipwrres23 at acpi0: FN00, resource for FAN0
acpipwrres24 at acpi0: FN01, resource for FAN1
acpipwrres25 at acpi0: FN02, resource for FAN2
acpipwrres26 at acpi0: FN03, resource for FAN3
acpipwrres27 at acpi0: FN04, resource for FAN4
acpitz0 at acpi0: critical temperature is 119 degC
acpitz1 at acpi0: critical temperature is 119 degC
acpivideo0 at acpi0: GFX0
acpivout0 at acpivideo0: DD1F
cpu0: using VERW MDS workaround (except on vmm entry)
cpu0: Enhanced SpeedStep 3393 MHz: speeds: 3401, 3400, 3200, 3000, 2800, 2700,
2500, 2300, 2100, 1900, 1700, 1500, 1400, 1200, 1000, 800 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 "Intel Core 6G Host" rev 0x07
ppb0 at pci0 dev 1 function 0 "Intel Core 6G PCIE" rev 0x07: msi
pci1 at ppb0 bus 1
inteldrm0 at pci0 dev 2 function 0 "Intel HD Graphics 530" rev 0x06
drm0 at inteldrm0
inteldrm0: msi, SKYLAKE, gen 9
xhci0 at pci0 dev 20 function 0 "Intel 100 Series xHCI" rev 0x31: msi, xHCI 1.0
usb0 at xhci0: USB revision 3.0
uhub0 at usb0 configuration 1 interface 0 "Intel xHCI root hub" rev 3.00/1.00
addr 1
pchtemp0 at pci0 dev 20 function 2 "Intel 100 Series Thermal" rev 0x31
"Intel 100 Series MEI" rev 0x31 at pci0 dev 22 function 0 not configured
puc0 at pci0 dev 22 function 3 "Intel 100 Series KT" rev 0x31: ports: 16 com
com4 at puc0 port 0 apic 2 int 19: ns16550a, 16 byte fifo
ahci0 at pci0 dev 23 function 0 "Intel 100 Series AHCI" rev 0x31: msi, AHCI
1.3.1
ahci0: port 0: 6.0Gb/s
ahci0: port 1: 1.5Gb/s
ahci0: PHY offline on port 2
ahci0: PHY offline on port 3
ahci0: port 4: 6.0Gb/s
scsibus1 at ahci0: 32 targets
sd0 at scsibus1 targ 0 lun 0: <ATA, TOSHIBA THNSNK25, K8DC> naa.500080d910a35c8a
sd0: 244198MB, 512 bytes/sector, 500118192 sectors, thin
cd0 at scsibus1 targ 1 lun 0: <HL-DT-ST, DVD+-RW GU90N, A1C1> removable
sd1 at scsibus1 targ 4 lun 0: <ATA, LITEON CV3-8D256, T884> naa.5002303100d391c3
sd1: 244198MB, 512 bytes/sector, 500118192 sectors, thin
pcib0 at pci0 dev 31 function 0 "Intel Q170 LPC" rev 0x31
"Intel 100 Series PMC" rev 0x31 at pci0 dev 31 function 2 not configured
azalia0 at pci0 dev 31 function 3 "Intel 100 Series HD Audio" rev 0x31: msi
azalia0: codecs: Realtek ALC255, Intel/0x2809, using Realtek ALC255
audio0 at azalia0
ichiic0 at pci0 dev 31 function 4 "Intel 100 Series SMBus" rev 0x31: apic 2 int
16
iic0 at ichiic0
spdmem0 at iic0 addr 0x50: 8GB DDR4 SDRAM PC4-17000
spdmem1 at iic0 addr 0x51: 8GB DDR4 SDRAM PC4-17000
spdmem2 at iic0 addr 0x52: 8GB DDR4 SDRAM PC4-17000
spdmem3 at iic0 addr 0x53: 8GB DDR4 SDRAM PC4-17000
em0 at pci0 dev 31 function 6 "Intel I219-LM" rev 0x31: msi, address
48:4d:7e:e4:58:58
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
pckbc0 at isa0 port 0x60/5 irq 1 irq 12
pckbd0 at pckbc0 (kbd slot)
wskbd0 at pckbd0: console keyboard
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
vmm0 at mainbus0: VMX/EPT
efifb at mainbus0 not configured
uhidev0 at uhub0 port 6 configuration 1 interface 0 "Gaming KB Gaming KB" rev
0.20/30.61 addr 2
uhidev0: iclass 3/1
ukbd0 at uhidev0: 8 variable keys, 6 key codes
wskbd1 at ukbd0 mux 1
uhidev1 at uhub0 port 6 configuration 1 interface 1 "Gaming KB Gaming KB" rev
0.20/30.61 addr 2
uhidev1: iclass 3/1, 8 report ids
uhid0 at uhidev1 reportid 1: input=1, output=0, feature=0
uhid1 at uhidev1 reportid 2: input=2, output=0, feature=0
uhid2 at uhidev1 reportid 5: input=0, output=0, feature=5
ukbd1 at uhidev1 reportid 6: 48 variable keys, 0 key codes
wskbd2 at ukbd1 mux 1
ukbd2 at uhidev1 reportid 7: 56 variable keys, 0 key codes
wskbd3 at ukbd2 mux 1
ukbd3 at uhidev1 reportid 8: 56 variable keys, 0 key codes
wskbd4 at ukbd3 mux 1
uhidev2 at uhub0 port 8 configuration 1 interface 0 "Logitech USB Receiver" rev
2.00/12.09 addr 3
uhidev2: iclass 3/1
ukbd4 at uhidev2: 8 variable keys, 6 key codes
wskbd5 at ukbd4 mux 1
uhidev3 at uhub0 port 8 configuration 1 interface 1 "Logitech USB Receiver" rev
2.00/12.09 addr 3
uhidev3: iclass 3/1, 8 report ids
ums0 at uhidev3 reportid 2: 16 buttons, Z and W dir
wsmouse0 at ums0 mux 0
uhid3 at uhidev3 reportid 3: input=4, output=0, feature=0
uhid4 at uhidev3 reportid 4: input=1, output=0, feature=0
uhid5 at uhidev3 reportid 8: input=1, output=0, feature=0
uhidev4 at uhub0 port 8 configuration 1 interface 2 "Logitech USB Receiver" rev
2.00/12.09 addr 3
uhidev4: iclass 3/0, 33 report ids
uhidpp0 at uhidev4 reportid 16 device 1 mouse "M570" serial ef-81-ff-80
uhid6 at uhidev4 reportid 32: input=14, output=14, feature=0
uhid7 at uhidev4 reportid 33: input=31, output=31, feature=0
vscsi0 at root
scsibus2 at vscsi0: 256 targets
softraid0 at root
scsibus3 at softraid0: 256 targets
root on sd0a (72b083e204d4e2ab.a) swap on sd0b dump on sd0b
inteldrm0: 1920x1080, 32bpp
wsdisplay0 at inteldrm0 mux 1: console (std, vt100 emulation), using wskbd0
wskbd1: connecting to wsdisplay0
wskbd2: connecting to wsdisplay0
wskbd3: connecting to wsdisplay0
wskbd4: connecting to wsdisplay0
wskbd5: connecting to wsdisplay0
wsdisplay0: screen 1-5 added (std, vt100 emulation)
On Tue, Feb 09, 2021 at 08:34:00AM +0100, Anton Lindqvist wrote:
> Hi,
>
> On Mon, Feb 08, 2021 at 02:50:39PM -0800, Anindya Mukherjee wrote:
> > Hi, I have a Logitech M570 which seems to be handled by this new driver.
> > However I don't see any battery level information.
> >
> > dmesg:
> > uhidpp0 at uhidev4 device 1 mouse "M570" serial ef-81-ff-80
> >
> > sysctl kern.version:
> > kern.version=OpenBSD 6.8-current (GENERIC.MP) #313: Fri Feb 5 18:31:44 MST
> > 2021
> > dera...@amd64.openbsd.org:/usr/src/sys/arch/amd64/compile/GENERIC.MP
> >
> > hw.sensors.uhidpp0 does not seem to exist.
> >
> > Regards,
> > Anindya
> >
>
> Could you try the following diff and send me the complete dmesg. I've
> also prepared an amd64 kernel with the patch applied:
>
> https://www.basename.se/tmp/bsd.uhidpp.battery
>
> diff --git sys/dev/usb/uhidpp.c sys/dev/usb/uhidpp.c
> index b041d86fecd..27f6137ec06 100644
> --- sys/dev/usb/uhidpp.c
> +++ sys/dev/usb/uhidpp.c
> @@ -29,7 +29,7 @@
> #include <dev/usb/usbdevs.h>
> #include <dev/usb/uhidev.h>
>
> -/* #define UHIDPP_DEBUG */
> +#define UHIDPP_DEBUG
> #ifdef UHIDPP_DEBUG
>
> #define DPRINTF(x...) do { \
> @@ -84,12 +84,16 @@ int uhidpp_debug = 1;
> #define HIDPP_GET_LONG_REGISTER 0x83
>
> #define HIDPP_REG_ENABLE_REPORTS 0x00
> +#define HIDPP_REG_BATTERY_STATUS 0x07
> #define HIDPP_REG_PAIRING_INFORMATION 0xb5
>
> #define HIDPP_NOTIF_DEVICE_BATTERY_STATUS (1 << 4)
> #define HIDPP_NOTIF_RECEIVER_WIRELESS (1 << 0)
> #define HIDPP_NOTIF_RECEIVER_SOFTWARE_PRESENT (1 << 3)
>
> +/* Number of battery levels supported by HID++ 1.0 devices. */
> +#define HIDPP_BATTERY_NLEVELS 7
> +
> /* HID++ 1.0 error codes. */
> #define HIDPP_ERROR 0x8f
> #define HIDPP_ERROR_SUCCESS 0x00
> @@ -112,7 +116,6 @@ int uhidpp_debug = 1;
> * greater than zero which is reserved for notifications.
> */
> #define HIDPP_SOFTWARE_ID 0x01
> -#define HIDPP_SOFTWARE_ID_MASK 0x0f
> #define HIDPP_SOFTWARE_ID_LEN 4
>
> #define HIDPP20_FEAT_ROOT_IDX 0x00
> @@ -154,8 +157,8 @@ int uhidpp_debug = 1;
>
> /* Feature access report used by the HID++ 2.0 (and greater) protocol. */
> struct fap {
> - uint8_t feature_index;
> - uint8_t funcindex_clientid;
> + uint8_t feature_idx;
> + uint8_t funcidx_swid;
> uint8_t params[HIDPP_REPORT_LONG_PARAMS_MAX];
> };
>
> @@ -185,6 +188,8 @@ struct uhidpp_notification {
> struct uhidpp_device {
> uint8_t d_id;
> uint8_t d_connected;
> + uint8_t d_major;
> + uint8_t d_minor;
> struct {
> struct ksensor b_sens[UHIDPP_NSENSORS];
> uint8_t b_feature_idx;
> @@ -237,8 +242,10 @@ struct uhidpp_notification
> *uhidpp_claim_notification(struct uhidpp_softc *);
> int uhidpp_consume_notification(struct uhidpp_softc *, struct uhidpp_report
> *);
> int uhidpp_is_notification(struct uhidpp_softc *, struct uhidpp_report *);
>
> -int hidpp_get_protocol_version(struct uhidpp_softc *, uint8_t, int *, int
> *);
> +int hidpp_get_protocol_version(struct uhidpp_softc *, uint8_t, uint8_t *,
> + uint8_t *);
>
> +int hidpp10_get_battery_status(struct uhidpp_softc *, uint8_t, uint8_t *);
> int hidpp10_get_name(struct uhidpp_softc *, uint8_t, char *, size_t);
> int hidpp10_get_serial(struct uhidpp_softc *, uint8_t, uint8_t *, size_t);
> int hidpp10_get_type(struct uhidpp_softc *, uint8_t, const char **);
> @@ -520,7 +527,7 @@ void
> uhidpp_device_connect(struct uhidpp_softc *sc, struct uhidpp_device *dev)
> {
> struct ksensor *sens;
> - int error, major, minor;
> + int error;
> uint8_t feature_type;
>
> MUTEX_ASSERT_LOCKED(&sc->sc_mtx);
> @@ -529,30 +536,40 @@ uhidpp_device_connect(struct uhidpp_softc *sc, struct
> uhidpp_device *dev)
> if (dev->d_connected)
> return;
>
> - error = hidpp_get_protocol_version(sc, dev->d_id, &major, &minor);
> + error = hidpp_get_protocol_version(sc, dev->d_id,
> + &dev->d_major, &dev->d_minor);
> if (error) {
> - DPRINTF("%s: protocol version failure: device_id=%d,
> error=%d\n",
> + DPRINTF("%s: protocol version failure: device_id=%d, "
> + "error=%d\n",
> __func__, dev->d_id, error);
> return;
> }
>
> DPRINTF("%s: device_id=%d, version=%d.%d\n",
> - __func__, dev->d_id, major, minor);
> + __func__, dev->d_id, dev->d_major, dev->d_minor);
>
> - error = hidpp20_root_get_feature(sc, dev->d_id,
> - HIDPP20_FEAT_BATTERY_IDX,
> - &dev->d_battery.b_feature_idx, &feature_type);
> - if (error) {
> - DPRINTF("%s: battery feature index failure: device_id=%d, "
> - "error=%d\n", __func__, dev->d_id, error);
> - return;
> - }
> + if (dev->d_major >= 2) {
> + error = hidpp20_root_get_feature(sc, dev->d_id,
> + HIDPP20_FEAT_BATTERY_IDX,
> + &dev->d_battery.b_feature_idx, &feature_type);
> + if (error) {
> + DPRINTF("%s: battery feature index failure: "
> + "device_id=%d, error=%d\n",
> + __func__, dev->d_id, error);
> + return;
> + }
>
> - error = hidpp20_battery_get_capability(sc, dev->d_id,
> - dev->d_battery.b_feature_idx, &dev->d_battery.b_nlevels);
> - if (error) {
> - DPRINTF("%s: battery capability failure: device_id=%d, "
> - "error=%d\n", __func__, dev->d_id, error);
> + error = hidpp20_battery_get_capability(sc, dev->d_id,
> + dev->d_battery.b_feature_idx, &dev->d_battery.b_nlevels);
> + if (error) {
> + DPRINTF("%s: battery capability failure: device_id=%d, "
> + "error=%d\n", __func__, dev->d_id, error);
> + return;
> + }
> +
> + } else if (dev->d_major == 1) {
> + dev->d_battery.b_nlevels = HIDPP_BATTERY_NLEVELS;
> + } else {
> return;
> }
>
> @@ -579,44 +596,58 @@ uhidpp_device_refresh(struct uhidpp_softc *sc, struct
> uhidpp_device *dev)
>
> MUTEX_ASSERT_LOCKED(&sc->sc_mtx);
>
> - error = hidpp20_battery_get_level_status(sc, dev->d_id,
> - dev->d_battery.b_feature_idx,
> - &dev->d_battery.b_level, &dev->d_battery.b_next_level,
> - &dev->d_battery.b_status);
> - if (error) {
> - DPRINTF("%s: battery level status failure: device_id=%d, "
> - "error=%d\n", __func__, dev->d_id, error);
> - return;
> - }
> + if (dev->d_major >= 2) {
> + error = hidpp20_battery_get_level_status(sc, dev->d_id,
> + dev->d_battery.b_feature_idx,
> + &dev->d_battery.b_level, &dev->d_battery.b_next_level,
> + &dev->d_battery.b_status);
> + if (error) {
> + DPRINTF("%s: battery status failure: device_id=%d, "
> + "error=%d\n",
> + __func__, dev->d_id, error);
> + return;
> + }
>
> - dev->d_battery.b_sens[0].value = dev->d_battery.b_level * 1000;
> - dev->d_battery.b_sens[0].flags &= ~SENSOR_FUNKNOWN;
> - if (dev->d_battery.b_nlevels < 10) {
> - /*
> - * According to the HID++ 2.0 specification, less than 10 levels
> - * should be mapped to the following 4 levels:
> - *
> - * [0, 10] critical
> - * [11, 30] low
> - * [31, 80] good
> - * [81, 100] full
> - *
> - * Since sensors are limited to 3 valid statuses, clamp it even
> - * further.
> - */
> - if (dev->d_battery.b_level <= 10)
> - dev->d_battery.b_sens[0].status = SENSOR_S_CRIT;
> - else if (dev->d_battery.b_level <= 30)
> - dev->d_battery.b_sens[0].status = SENSOR_S_WARN;
> - else
> - dev->d_battery.b_sens[0].status = SENSOR_S_OK;
> + dev->d_battery.b_sens[0].value = dev->d_battery.b_level * 1000;
> + dev->d_battery.b_sens[0].flags &= ~SENSOR_FUNKNOWN;
> + if (dev->d_battery.b_nlevels < 10) {
> + /*
> + * According to the HID++ 2.0 specification, less than
> + * 10 levels should be mapped to the following 4 levels:
> + *
> + * [0, 10] critical
> + * [11, 30] low
> + * [31, 80] good
> + * [81, 100] full
> + *
> + * Since sensors are limited to 3 valid statuses, clamp
> + * it even further.
> + */
> + if (dev->d_battery.b_level <= 10)
> + dev->d_battery.b_sens[0].status = SENSOR_S_CRIT;
> + else if (dev->d_battery.b_level <= 30)
> + dev->d_battery.b_sens[0].status = SENSOR_S_WARN;
> + else
> + dev->d_battery.b_sens[0].status = SENSOR_S_OK;
> + } else {
> + /*
> + * XXX the device supports battery mileage. The current
> + * level must be checked against resp.fap.params[3]
> + * given by hidpp20_battery_get_capability().
> + */
> + dev->d_battery.b_sens[0].status = SENSOR_S_UNKNOWN;
> + }
> } else {
> - /*
> - * XXX the device supports battery mileage. The current level
> - * must be checked against resp.fap.params[3] given by
> - * hidpp20_battery_get_capability().
> - */
> - dev->d_battery.b_sens[0].status = SENSOR_S_UNKNOWN;
> + error = hidpp10_get_battery_status(sc, dev->d_id,
> + &dev->d_battery.b_level);
> + if (error) {
> + DPRINTF("%s: battery status failure: device_id=%d, "
> + "error=%d\n",
> + __func__, dev->d_id, error);
> + return;
> + }
> + dev->d_battery.b_sens[0].value = dev->d_battery.b_level * 1000;
> + dev->d_battery.b_sens[0].flags &= ~SENSOR_FUNKNOWN;
> }
> }
>
> @@ -692,9 +723,9 @@ uhidpp_is_notification(struct uhidpp_softc *sc, struct
> uhidpp_report *rep)
>
> /* An error must always be a response. */
> if ((rep->rap.sub_id == HIDPP_ERROR ||
> - rep->fap.feature_index == HIDPP20_ERROR) &&
> - rep->fap.funcindex_clientid == sc->sc_req->fap.feature_index &&
> - rep->fap.params[0] == sc->sc_req->fap.funcindex_clientid)
> + rep->fap.feature_idx == HIDPP20_ERROR) &&
> + rep->fap.funcidx_swid == sc->sc_req->fap.feature_idx &&
> + rep->fap.params[0] == sc->sc_req->fap.funcidx_swid)
> return 0;
>
> return 1;
> @@ -702,7 +733,7 @@ uhidpp_is_notification(struct uhidpp_softc *sc, struct
> uhidpp_report *rep)
>
> int
> hidpp_get_protocol_version(struct uhidpp_softc *sc, uint8_t device_id,
> - int *major, int *minor)
> + uint8_t *major, uint8_t *minor)
> {
> struct uhidpp_report resp;
> uint8_t params[3] = { 0, 0, HIDPP_FEAT_ROOT_PING_DATA };
> @@ -729,6 +760,37 @@ hidpp_get_protocol_version(struct uhidpp_softc *sc,
> uint8_t device_id,
> return 0;
> }
>
> +int
> +hidpp10_get_battery_status(struct uhidpp_softc *sc, uint8_t device_id,
> + uint8_t *level)
> +{
> + struct uhidpp_report resp;
> + int error;
> +
> + error = hidpp_send_rap_report(sc,
> + HIDPP_REPORT_ID_SHORT,
> + device_id,
> + HIDPP_GET_REGISTER,
> + HIDPP_REG_BATTERY_STATUS,
> + NULL, 0, &resp);
> + DPRINTF("XXX %s: error=%d, device_id=%d\n",
> + __func__, error, device_id);
> + if (error)
> + return error;
> + if (resp.rap.params[0] < 1 ||
> + resp.rap.params[0] > HIDPP_BATTERY_NLEVELS)
> + return -ERANGE;
> +
> + DPRINTF("XXX %s: p0=%x, p1=%x, p2=%x, device_id=%d\n",
> + __func__,
> + resp.rap.params[0],
> + resp.rap.params[1],
> + resp.rap.params[2],
> + device_id);
> + *level = (resp.rap.params[0] * 100) / HIDPP_BATTERY_NLEVELS;
> + return 0;
> +}
> +
> int
> hidpp10_get_name(struct uhidpp_softc *sc, uint8_t device_id,
> char *buf, size_t bufsiz)
> @@ -848,7 +910,7 @@ hidpp10_enable_notifications(struct uhidpp_softc *sc,
> uint8_t device_id)
>
> int
> hidpp20_root_get_feature(struct uhidpp_softc *sc, uint8_t device_id,
> - uint16_t feature, uint8_t *feature_index, uint8_t *feature_type)
> + uint16_t feature, uint8_t *feature_idx, uint8_t *feature_type)
> {
> struct uhidpp_report resp;
> uint8_t params[2] = { feature >> 8, feature & 0xff };
> @@ -866,14 +928,14 @@ hidpp20_root_get_feature(struct uhidpp_softc *sc,
> uint8_t device_id,
> if (resp.fap.params[0] == 0)
> return -ENOENT;
>
> - *feature_index = resp.fap.params[0];
> + *feature_idx = resp.fap.params[0];
> *feature_type = resp.fap.params[1];
> return 0;
> }
>
> int
> hidpp20_battery_get_level_status(struct uhidpp_softc *sc, uint8_t device_id,
> - uint8_t feature_index, uint8_t *level, uint8_t *next_level, uint8_t
> *status)
> + uint8_t feature_idx, uint8_t *level, uint8_t *next_level, uint8_t
> *status)
> {
> struct uhidpp_report resp;
> int error;
> @@ -881,7 +943,7 @@ hidpp20_battery_get_level_status(struct uhidpp_softc *sc,
> uint8_t device_id,
> error = hidpp_send_fap_report(sc,
> HIDPP_REPORT_ID_LONG,
> device_id,
> - feature_index,
> + feature_idx,
> HIDPP20_FEAT_BATTERY_LEVEL_FUNC,
> NULL, 0, &resp);
> if (error)
> @@ -895,7 +957,7 @@ hidpp20_battery_get_level_status(struct uhidpp_softc *sc,
> uint8_t device_id,
>
> int
> hidpp20_battery_get_capability(struct uhidpp_softc *sc, uint8_t device_id,
> - uint8_t feature_index, uint8_t *nlevels)
> + uint8_t feature_idx, uint8_t *nlevels)
> {
> struct uhidpp_report resp;
> int error;
> @@ -903,7 +965,7 @@ hidpp20_battery_get_capability(struct uhidpp_softc *sc,
> uint8_t device_id,
> error = hidpp_send_fap_report(sc,
> HIDPP_REPORT_ID_LONG,
> device_id,
> - feature_index,
> + feature_idx,
> HIDPP20_FEAT_BATTERY_CAPABILITY_FUNC,
> NULL, 0, &resp);
> if (error)
> @@ -929,7 +991,7 @@ hidpp_send_validate(uint8_t report_id, int nparams)
>
> int
> hidpp_send_fap_report(struct uhidpp_softc *sc, uint8_t report_id,
> - uint8_t device_id, uint8_t feature_index, uint8_t funcindex_clientid,
> + uint8_t device_id, uint8_t feature_idx, uint8_t funcidx_swid,
> uint8_t *params, int nparams, struct uhidpp_report *resp)
> {
> struct uhidpp_report req;
> @@ -941,9 +1003,9 @@ hidpp_send_fap_report(struct uhidpp_softc *sc, uint8_t
> report_id,
>
> memset(&req, 0, sizeof(req));
> req.device_id = device_id;
> - req.fap.feature_index = feature_index;
> - req.fap.funcindex_clientid =
> - (funcindex_clientid << HIDPP_SOFTWARE_ID_LEN) | HIDPP_SOFTWARE_ID;
> + req.fap.feature_idx = feature_idx;
> + req.fap.funcidx_swid =
> + (funcidx_swid << HIDPP_SOFTWARE_ID_LEN) | HIDPP_SOFTWARE_ID;
> memcpy(req.fap.params, params, nparams);
> return hidpp_send_report(sc, report_id, &req, resp);
> }
> @@ -1024,7 +1086,7 @@ hidpp_send_report(struct uhidpp_softc *sc, uint8_t
> report_id,
> resp->rap.sub_id == HIDPP_ERROR)
> error = resp->rap.params[1];
> else if (sc->sc_resp_state == HIDPP_REPORT_ID_LONG &&
> - resp->fap.feature_index == HIDPP20_ERROR)
> + resp->fap.feature_idx == HIDPP20_ERROR)
> error = resp->fap.params[1];
>
> out:
