This adds a basic driver (glue) for the Cadence SD/SDIO/eMMC
host controller.
The controller is mostly SDHC compatible. However, the SDHC register
set is at an offset from the start of the register region. In addition,
the controller handles card detect through SDHC registers, and will
probably need extra code for tuning for higher speed modes. Therefore
I have added a separate driver module, instead of tweaking sdhc_fdt.c.
OK?
Index: share/man/man4/Makefile
===================================================================
RCS file: src/share/man/man4/Makefile,v
retrieving revision 1.816
diff -u -p -r1.816 Makefile
--- share/man/man4/Makefile 10 Jan 2022 04:59:19 -0000 1.816
+++ share/man/man4/Makefile 14 Jan 2022 17:12:53 -0000
@@ -24,7 +24,7 @@ MAN= aac.4 abcrtc.4 abl.4 ac97.4 acphy.4
berkwdt.4 bge.4 bgw.4 bio.4 bpe.4 bktr.4 bmtphy.4 bnx.4 bnxt.4 \
boca.4 bpf.4 brgphy.4 bridge.4 brswphy.4 bse.4 bwfm.4 bwi.4 bytgpio.4 \
cac.4 cad.4 cas.4 cardbus.4 carp.4 ccp.4 ccpmic.4 cd.4 cdce.4 \
- cduart.4 cfxga.4 \
+ cdsdhc.4 cduart.4 cfxga.4 \
ch.4 chvgpio.4 ciphy.4 ciss.4 clcs.4 clct.4 cmpci.4 \
com.4 cue.4 cwfg.4 cy.4 cz.4 \
dapmic.4 \
Index: share/man/man4/cdsdhc.4
===================================================================
RCS file: share/man/man4/cdsdhc.4
diff -N share/man/man4/cdsdhc.4
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ share/man/man4/cdsdhc.4 14 Jan 2022 17:12:53 -0000
@@ -0,0 +1,40 @@
+.\" $OpenBSD$
+.\"
+.\" Copyright (c) 2022 Visa Hankala
+.\"
+.\" Permission to use, copy, modify, and distribute this software for any
+.\" purpose with or without fee is hereby granted, provided that the above
+.\" copyright notice and this permission notice appear in all copies.
+.\"
+.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+.\"
+.Dd $Mdocdate$
+.Dt CDSDHC 4
+.Os
+.Sh NAME
+.Nm cdsdhc
+.Nd Cadence SD/SDIO/eMMC host controller
+.Sh SYNOPSIS
+.Cd "cdsdhc* at fdt?"
+.Cd "sdmmc* at cdsdhc?"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for the Cadence SD/SDIO/eMMC host controller,
+which provides an interface to the
+.Xr sdmmc 4
+bus.
+.Sh SEE ALSO
+.Xr intro 4 ,
+.Xr sdmmc 4
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Ox 7.1 .
Index: sys/arch/riscv64/conf/GENERIC
===================================================================
RCS file: src/sys/arch/riscv64/conf/GENERIC,v
retrieving revision 1.32
diff -u -p -r1.32 GENERIC
--- sys/arch/riscv64/conf/GENERIC 5 Jan 2022 03:32:44 -0000 1.32
+++ sys/arch/riscv64/conf/GENERIC 14 Jan 2022 17:12:54 -0000
@@ -45,6 +45,8 @@ intc0 at cpu0
com* at fdt?
# PolarFire SoCs
+cdsdhc* at fdt?
+sdmmc* at cdsdhc?
mpfclock* at fdt? early 1
# SiFive SoCs
Index: sys/arch/riscv64/conf/RAMDISK
===================================================================
RCS file: src/sys/arch/riscv64/conf/RAMDISK,v
retrieving revision 1.28
diff -u -p -r1.28 RAMDISK
--- sys/arch/riscv64/conf/RAMDISK 5 Jan 2022 03:32:44 -0000 1.28
+++ sys/arch/riscv64/conf/RAMDISK 14 Jan 2022 17:12:54 -0000
@@ -36,6 +36,8 @@ intc0 at cpu0
com* at fdt?
# PolarFire SoCs
+cdsdhc* at fdt?
+sdmmc* at cdsdhc?
mpfclock* at fdt? early 1
# SiFive SoCs
Index: sys/dev/fdt/cdsdhc.c
===================================================================
RCS file: sys/dev/fdt/cdsdhc.c
diff -N sys/dev/fdt/cdsdhc.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ sys/dev/fdt/cdsdhc.c 14 Jan 2022 17:12:54 -0000
@@ -0,0 +1,168 @@
+/* $OpenBSD$ */
+
+/*
+ * Copyright (c) 2022 Visa Hankala
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver glue for Cadence SD/SDIO/eMMC host controller.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/conf.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+#include <machine/fdt.h>
+
+#include <dev/ofw/fdt.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_clock.h>
+
+#include <dev/sdmmc/sdhcvar.h>
+#include <dev/sdmmc/sdmmcvar.h>
+
+/* Host Register Set */
+#define HRS06 0x0018
+#define HRS06_ETR (0x1 << 15)
+#define HRS06_ETV_MASK (0x3f << 8)
+#define HRS06_ETV_SHIFT 8
+#define HRS06_EMM_MASK (0x7 << 0)
+#define HRS06_EMM_SD (0x0 << 0)
+#define HRS06_EMM_MMC_SDR (0x2 << 0)
+#define HRS06_EMM_MMC_DDR (0x3 << 0)
+#define HRS06_EMM_MMC_HS200 (0x4 << 0)
+#define HRS06_EMM_MMC_HS400 (0x5 << 0)
+#define HRS06_EMM_MMC_HS400_ENH (0x6 << 0)
+#define HRS31 0x007c
+#define HRS31_HOSTCTLVER(x) (((x) >> 16) & 0xfff)
+#define HRS31_HOSTFIXVER(x) ((x) & 0xff)
+
+/* Slot Register Set */
+#define SRS_OFFSET 0x200
+#define SRS_SIZE 0x100
+
+struct cdsdhc_softc {
+ struct sdhc_softc sc_sdhc;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+ bus_space_handle_t sc_srs_ioh;
+ void *sc_ih;
+
+ struct sdhc_host *sc_host;
+};
+
+#define HREAD4(sc, reg) \
+ (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
+#define HWRITE4(sc, reg, val) \
+ bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+
+int cdsdhc_match(struct device *, void *, void*);
+void cdsdhc_attach(struct device *, struct device *, void *);
+void cdsdhc_bus_clock_pre(struct sdhc_softc *, int, int);
+
+const struct cfattach cdsdhc_ca = {
+ sizeof(struct cdsdhc_softc), cdsdhc_match, cdsdhc_attach
+};
+
+struct cfdriver cdsdhc_cd = {
+ NULL, "cdsdhc", DV_DULL
+};
+
+int
+cdsdhc_match(struct device *parent, void *match, void *aux)
+{
+ struct fdt_attach_args *faa = aux;
+
+ if (faa->fa_nreg < 1)
+ return 0;
+ return OF_is_compatible(faa->fa_node, "cdns,sd4hc");
+}
+
+void
+cdsdhc_attach(struct device *parent, struct device *self, void *aux)
+{
+ struct fdt_attach_args *faa = aux;
+ struct cdsdhc_softc *sc = (struct cdsdhc_softc *)self;
+ uint32_t caps = 0;
+ uint32_t ver;
+
+ sc->sc_iot = faa->fa_iot;
+
+ if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, faa->fa_reg[0].size,
+ 0, &sc->sc_ioh) != 0) {
+ printf(": can't map registers\n");
+ return;
+ }
+
+ if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, SRS_OFFSET, SRS_SIZE,
+ &sc->sc_srs_ioh) != 0) {
+ printf(": can't map SRS subregion\n");
+ goto unmap;
+ }
+
+ clock_enable_all(faa->fa_node);
+
+ sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO,
+ sdhc_intr, sc, sc->sc_sdhc.sc_dev.dv_xname);
+ if (sc->sc_ih == NULL) {
+ printf(": can't establish interrupt\n");
+ goto disable;
+ }
+
+ ver = HREAD4(sc, HRS31);
+ printf(": rev 0x%x/0x%x\n", HRS31_HOSTCTLVER(ver),
+ HRS31_HOSTFIXVER(ver));
+
+ sc->sc_sdhc.sc_host = &sc->sc_host;
+ sc->sc_sdhc.sc_dmat = faa->fa_dmat;
+ sc->sc_sdhc.sc_bus_clock_pre = cdsdhc_bus_clock_pre;
+ sdhc_host_found(&sc->sc_sdhc, sc->sc_iot, sc->sc_srs_ioh, SRS_SIZE,
+ 1, caps);
+ return;
+
+disable:
+ clock_disable_all(faa->fa_node);
+unmap:
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size);
+}
+
+void
+cdsdhc_bus_clock_pre(struct sdhc_softc *sc_sdhc, int freq, int timing)
+{
+ struct cdsdhc_softc *sc = (struct cdsdhc_softc *)sc_sdhc;
+ uint32_t mode, val;
+
+ switch (timing) {
+ case SDMMC_TIMING_HIGHSPEED:
+ mode = HRS06_EMM_MMC_SDR;
+ break;
+ case SDMMC_TIMING_MMC_DDR52:
+ mode = HRS06_EMM_MMC_DDR;
+ break;
+ case SDMMC_TIMING_MMC_HS200:
+ mode = HRS06_EMM_MMC_HS200;
+ break;
+ default:
+ mode = HRS06_EMM_SD;
+ break;
+ }
+
+ val = HREAD4(sc, HRS06);
+ val &= ~HRS06_EMM_MASK;
+ val |= mode;
+ HWRITE4(sc, HRS06, val);
+}
Index: sys/dev/fdt/files.fdt
===================================================================
RCS file: src/sys/dev/fdt/files.fdt,v
retrieving revision 1.160
diff -u -p -r1.160 files.fdt
--- sys/dev/fdt/files.fdt 21 Nov 2021 11:02:21 -0000 1.160
+++ sys/dev/fdt/files.fdt 14 Jan 2022 17:12:54 -0000
@@ -289,6 +289,10 @@ device cad: ether, ifnet, mii, ifmedia
attach cad at fdt
file dev/fdt/if_cad.c cad
+device cdsdhc: sdmmcbus, sdhc
+attach cdsdhc at fdt
+file dev/fdt/cdsdhc.c cdsdhc
+
device cduart
attach cduart at fdt
file dev/fdt/cduart.c cduart
