Hi,
At the urging of sthen@ and dv@, here is v5.
Two major changes from v4:
- Add the function tc_reset_quality() to kern_tc.c and use it
to lower the quality of the TSC timecounter if we fail the
sync test.
tc_reset_quality() will choose a new active timecounter if,
after the quality change, the given timecounter is no longer
the best timecounter.
The upshot is: if you fail the TSC sync test you should boot
with the HPET as your active timecounter. If you don't have
an HPET you'll be using something else.
- Drop the SMT accomodation from the hot loop. It hasn't been
necessary since last year when I rewrote the test to run without
a mutex. In the rewritten test, the two CPUs in the hot loop
are not competing for any resources so they should not be able
to starve one another.
dv: Could you double-check that this still chooses the right
timecounter on your machine? If so, I will ask deraadt@ to
put this into snaps to replace v4.
Additional test reports are welcome. Include your dmesg.
--
I do not see much more I can do to improve this patch.
I am seeking patch review and OKs.
I am especially interested in whether my assumptions in tsc_ap_test()
and tsc_bp_test() are correct. The whole patch depends on those
assumptions. Is this a valid way to test for TSC desync? Or am I
missing membar_producer()/membar_consumer() calls?
Here is the long version of "what" and "why" for this patch.
The patch is attached at the end.
- Computing a per-CPU TSC skew value is error-prone, especially
on multisocket machines and VMs. My best guess is that larger
latencies appear to the skew measurement test as TSC desync,
and so the TSC is demoted to a kernel timecounter on these
machines or marked non-monotonic.
This patch eliminates per-CPU TSC skew values. Instead of trying
to measure and correct for TSC desync we only try to detect desync,
which is less error-prone. This approach should allow a wider
variety of machines to use the TSC as a timecounter when running
OpenBSD.
- In the new sync test, both CPUs repeatedly try to detect whether
their TSC is trailing the other CPU's TSC. The upside to this
approach is that it yields no false positives (if my assumptions
about AMD64 memory access and instruction serialization are correct).
The downside to this approach is that it takes more time than the
current skew measurement test. Each test round takes 1ms, and
we run up to two rounds per CPU, so this patch slows boot down
by 2ms per AP.
- If any CPU fails the sync test, the TSC is marked non-monotonic
and a different timecounter is activated. The TC_USER flag
remains intact. There is no "middle ground" where we fall back
to only using the TSC in the kernel.
- Because there is no per-CPU skew value, there is also no concept
of TSC drift anymore.
- Before running the test, we check for the IA32_TSC_ADJUST
register and reset it if necessary. This is a trivial way
to work around firmware bugs that desync the TSC before we
reach the kernel.
Unfortunately, at the moment this register appears to only
be available on Intel processors and I cannot find an equivalent
but differently-named MSR for AMD processors.
--
Index: sys/arch/amd64/amd64/tsc.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/tsc.c,v
retrieving revision 1.24
diff -u -p -r1.24 tsc.c
--- sys/arch/amd64/amd64/tsc.c 31 Aug 2021 15:11:54 -0000 1.24
+++ sys/arch/amd64/amd64/tsc.c 31 Jul 2022 03:06:39 -0000
@@ -36,13 +36,6 @@ int tsc_recalibrate;
uint64_t tsc_frequency;
int tsc_is_invariant;
-#define TSC_DRIFT_MAX 250
-#define TSC_SKEW_MAX 100
-int64_t tsc_drift_observed;
-
-volatile int64_t tsc_sync_val;
-volatile struct cpu_info *tsc_sync_cpu;
-
u_int tsc_get_timecount(struct timecounter *tc);
void tsc_delay(int usecs);
@@ -236,22 +229,12 @@ cpu_recalibrate_tsc(struct timecounter *
u_int
tsc_get_timecount(struct timecounter *tc)
{
- return rdtsc_lfence() + curcpu()->ci_tsc_skew;
+ return rdtsc_lfence();
}
void
tsc_timecounter_init(struct cpu_info *ci, uint64_t cpufreq)
{
-#ifdef TSC_DEBUG
- printf("%s: TSC skew=%lld observed drift=%lld\n", ci->ci_dev->dv_xname,
- (long long)ci->ci_tsc_skew, (long long)tsc_drift_observed);
-#endif
- if (ci->ci_tsc_skew < -TSC_SKEW_MAX || ci->ci_tsc_skew > TSC_SKEW_MAX) {
- printf("%s: disabling user TSC (skew=%lld)\n",
- ci->ci_dev->dv_xname, (long long)ci->ci_tsc_skew);
- tsc_timecounter.tc_user = 0;
- }
-
if (!(ci->ci_flags & CPUF_PRIMARY) ||
!(ci->ci_flags & CPUF_CONST_TSC) ||
!(ci->ci_flags & CPUF_INVAR_TSC))
@@ -268,111 +251,264 @@ tsc_timecounter_init(struct cpu_info *ci
calibrate_tsc_freq();
}
- if (tsc_drift_observed > TSC_DRIFT_MAX) {
- printf("ERROR: %lld cycle TSC drift observed\n",
- (long long)tsc_drift_observed);
- tsc_timecounter.tc_quality = -1000;
- tsc_timecounter.tc_user = 0;
- tsc_is_invariant = 0;
- }
-
tc_init(&tsc_timecounter);
}
-/*
- * Record drift (in clock cycles). Called during AP startup.
- */
void
-tsc_sync_drift(int64_t drift)
+tsc_delay(int usecs)
{
- if (drift < 0)
- drift = -drift;
- if (drift > tsc_drift_observed)
- tsc_drift_observed = drift;
+ uint64_t interval, start;
+
+ interval = (uint64_t)usecs * tsc_frequency / 1000000;
+ start = rdtsc_lfence();
+ while (rdtsc_lfence() - start < interval)
+ CPU_BUSY_CYCLE();
}
+#ifdef MULTIPROCESSOR
+
+#define TSC_DEBUG 1
+
+/*
+ * Protections for global variables in this code:
+ *
+ * a Modified atomically
+ * b Protected by a barrier
+ * p Only modified by the primary CPU
+ */
+
+#define TSC_TEST_MSECS 1 /* Test round duration */
+#define TSC_TEST_ROUNDS 2 /* Number of test rounds */
+
/*
- * Called during startup of APs, by the boot processor. Interrupts
- * are disabled on entry.
+ * tsc_test_status.val is isolated to its own cache line to limit
+ * false sharing and reduce the test's margin of error.
*/
+struct tsc_test_status {
+ volatile uint64_t val; /* [a] Latest RDTSC value */
+ uint64_t pad1[7];
+ uint64_t lag_count; /* [b] Number of lags seen by CPU */
+ uint64_t lag_max; /* [b] Biggest lag seen by CPU */
+ int64_t adj; /* [b] Initial IA32_TSC_ADJUST value */
+ uint64_t pad2[5];
+} __aligned(64);
+struct tsc_test_status tsc_ap_status; /* Test results from AP */
+struct tsc_test_status tsc_bp_status; /* Test results from BP */
+uint64_t tsc_test_cycles; /* [p] TSC cycles per test round */
+const char *tsc_ap_name; /* [b] Name of AP running test */
+volatile u_int tsc_egress_barrier; /* [a] Test end barrier */
+volatile u_int tsc_ingress_barrier; /* [a] Test start barrier */
+volatile u_int tsc_test_rounds; /* [p] Remaining test rounds */
+int tsc_is_synchronized = 1; /* [p] Have we ever failed the test? */
+
+void tsc_report_test_results(void);
+void tsc_reset_adjust(struct tsc_test_status *);
+void tsc_test_ap(void);
+void tsc_test_bp(void);
+
void
-tsc_read_bp(struct cpu_info *ci, uint64_t *bptscp, uint64_t *aptscp)
+tsc_test_sync_bp(struct cpu_info *ci)
{
- uint64_t bptsc;
-
- if (atomic_swap_ptr(&tsc_sync_cpu, ci) != NULL)
- panic("tsc_sync_bp: 1");
+ if (!tsc_is_invariant)
+ return;
+#ifndef TSC_DEBUG
+ /* No point in testing again if we already failed. */
+ if (!tsc_is_synchronized)
+ return;
+#endif
+ /* Reset IA32_TSC_ADJUST if it exists. */
+ tsc_reset_adjust(&tsc_bp_status);
- /* Flag it and read our TSC. */
- atomic_setbits_int(&ci->ci_flags, CPUF_SYNCTSC);
- bptsc = (rdtsc_lfence() >> 1);
+ /* Reset the test cycle limit and round count. */
+ tsc_test_cycles = TSC_TEST_MSECS * tsc_frequency / 1000;
+ tsc_test_rounds = TSC_TEST_ROUNDS;
+
+ do {
+ /*
+ * Pass through the ingress barrier, run the test,
+ * then wait for the AP to reach the egress barrier.
+ */
+ atomic_inc_int(&tsc_ingress_barrier);
+ while (tsc_ingress_barrier != 2)
+ CPU_BUSY_CYCLE();
+ tsc_test_bp();
+ while (tsc_egress_barrier != 1)
+ CPU_BUSY_CYCLE();
+
+ /*
+ * Report what happened. Adjust the TSC's quality
+ * if this is the first time we've failed the test.
+ */
+ tsc_report_test_results();
+ if (tsc_ap_status.lag_count || tsc_bp_status.lag_count) {
+ if (tsc_is_synchronized) {
+ tsc_is_synchronized = 0;
+ tc_reset_quality(&tsc_timecounter, -1000);
+ }
+ tsc_test_rounds = 0;
+ } else
+ tsc_test_rounds--;
+
+ /*
+ * Clean up for the next round. It is safe to reset the
+ * ingress barrier because at this point we know the AP
+ * has reached the egress barrier.
+ */
+ memset(&tsc_ap_status, 0, sizeof tsc_ap_status);
+ memset(&tsc_bp_status, 0, sizeof tsc_bp_status);
+ tsc_ingress_barrier = 0;
+ if (tsc_test_rounds == 0)
+ tsc_ap_name = NULL;
+
+ /*
+ * Pass through the egress barrier and release the AP.
+ * The AP is responsible for resetting the egress barrier.
+ */
+ if (atomic_inc_int_nv(&tsc_egress_barrier) != 2)
+ panic("%s: unexpected egress count", __func__);
+ } while (tsc_test_rounds > 0);
+}
- /* Wait for remote to complete, and read ours again. */
- while ((ci->ci_flags & CPUF_SYNCTSC) != 0)
- membar_consumer();
- bptsc += (rdtsc_lfence() >> 1);
+void
+tsc_test_sync_ap(struct cpu_info *ci)
+{
+ if (!tsc_is_invariant)
+ return;
+#ifndef TSC_DEBUG
+ if (!tsc_is_synchronized)
+ return;
+#endif
+ /* The BP needs our name in order to report any problems. */
+ if (atomic_cas_ptr(&tsc_ap_name, NULL, ci->ci_dev->dv_xname) != NULL) {
+ panic("%s: %s: tsc_ap_name is not NULL: %s",
+ __func__, ci->ci_dev->dv_xname, tsc_ap_name);
+ }
- /* Wait for the results to come in. */
- while (tsc_sync_cpu == ci)
- CPU_BUSY_CYCLE();
- if (tsc_sync_cpu != NULL)
- panic("tsc_sync_bp: 2");
+ tsc_reset_adjust(&tsc_ap_status);
- *bptscp = bptsc;
- *aptscp = tsc_sync_val;
+ /*
+ * The AP is only responsible for running the test and
+ * resetting the egress barrier. The BP handles everything
+ * else.
+ */
+ do {
+ atomic_inc_int(&tsc_ingress_barrier);
+ while (tsc_ingress_barrier != 2)
+ CPU_BUSY_CYCLE();
+ tsc_test_ap();
+ atomic_inc_int(&tsc_egress_barrier);
+ while (atomic_cas_uint(&tsc_egress_barrier, 2, 0) != 2)
+ CPU_BUSY_CYCLE();
+ } while (tsc_test_rounds > 0);
}
void
-tsc_sync_bp(struct cpu_info *ci)
+tsc_report_test_results(void)
{
- uint64_t bptsc, aptsc;
-
- tsc_read_bp(ci, &bptsc, &aptsc); /* discarded - cache effects */
- tsc_read_bp(ci, &bptsc, &aptsc);
+ u_int round = TSC_TEST_ROUNDS - tsc_test_rounds + 1;
- /* Compute final value to adjust for skew. */
- ci->ci_tsc_skew = bptsc - aptsc;
+ if (tsc_bp_status.adj != 0) {
+ printf("tsc: cpu0: IA32_TSC_ADJUST: %lld -> 0\n",
+ tsc_bp_status.adj);
+ }
+ if (tsc_ap_status.adj != 0) {
+ printf("tsc: %s: IA32_TSC_ADJUST: %lld -> 0\n",
+ tsc_ap_name, tsc_ap_status.adj);
+ }
+ if (tsc_ap_status.lag_count > 0 || tsc_bp_status.lag_count > 0) {
+ printf("tsc: cpu0/%s: sync test round %u/%u failed\n",
+ tsc_ap_name, round, TSC_TEST_ROUNDS);
+ }
+ if (tsc_bp_status.lag_count > 0) {
+ printf("tsc: cpu0/%s: cpu0: %llu lags %llu cycles\n",
+ tsc_ap_name, tsc_bp_status.lag_count,
+ tsc_bp_status.lag_max);
+ }
+ if (tsc_ap_status.lag_count > 0) {
+ printf("tsc: cpu0/%s: %s: %llu lags %llu cycles\n",
+ tsc_ap_name, tsc_ap_name, tsc_ap_status.lag_count,
+ tsc_ap_status.lag_max);
+ }
}
/*
- * Called during startup of AP, by the AP itself. Interrupts are
- * disabled on entry.
+ * Reset IA32_TSC_ADJUST if we have it.
+ *
+ * XXX We should rearrange cpu_hatch() so that the feature
+ * flags are already set before we get here. Check CPUID
+ * by hand until then.
*/
void
-tsc_post_ap(struct cpu_info *ci)
+tsc_reset_adjust(struct tsc_test_status *tts)
{
- uint64_t tsc;
-
- /* Wait for go-ahead from primary. */
- while ((ci->ci_flags & CPUF_SYNCTSC) == 0)
- membar_consumer();
- tsc = (rdtsc_lfence() >> 1);
+ uint32_t eax, ebx, ecx, edx;
- /* Instruct primary to read its counter. */
- atomic_clearbits_int(&ci->ci_flags, CPUF_SYNCTSC);
- tsc += (rdtsc_lfence() >> 1);
-
- /* Post result. Ensure the whole value goes out atomically. */
- (void)atomic_swap_64(&tsc_sync_val, tsc);
-
- if (atomic_swap_ptr(&tsc_sync_cpu, NULL) != ci)
- panic("tsc_sync_ap");
+ CPUID(0, eax, ebx, ecx, edx);
+ if (eax >= 7) {
+ CPUID_LEAF(7, 0, eax, ebx, ecx, edx);
+ if (ISSET(ebx, SEFF0EBX_TSC_ADJUST)) {
+ tts->adj = rdmsr(MSR_TSC_ADJUST);
+ if (tts->adj != 0)
+ wrmsr(MSR_TSC_ADJUST, 0);
+ }
+ }
}
void
-tsc_sync_ap(struct cpu_info *ci)
+tsc_test_ap(void)
{
- tsc_post_ap(ci);
- tsc_post_ap(ci);
+ uint64_t ap_val, bp_val, end, lag;
+
+ ap_val = rdtsc_lfence();
+ end = ap_val + tsc_test_cycles;
+ while (__predict_false(ap_val < end)) {
+ /*
+ * Get the BP's latest TSC value, then read the AP's
+ * TSC. LFENCE is a serializing instruction, so we
+ * know bp_val predates ap_val. If ap_val is smaller
+ * than bp_val then the AP's TSC must trail that of
+ * the BP and the counters cannot be synchronized.
+ */
+ bp_val = tsc_bp_status.val;
+ ap_val = rdtsc_lfence();
+ tsc_ap_status.val = ap_val;
+
+ /*
+ * Record the magnitude of the problem if the AP's TSC
+ * trails the BP's TSC.
+ */
+ if (__predict_false(ap_val < bp_val)) {
+ tsc_ap_status.lag_count++;
+ lag = bp_val - ap_val;
+ if (tsc_ap_status.lag_max < lag)
+ tsc_ap_status.lag_max = lag;
+ }
+ }
}
+/*
+ * This is similar to tsc_test_ap(), but with all relevant variables
+ * flipped around to run the test from the BP's perspective.
+ */
void
-tsc_delay(int usecs)
+tsc_test_bp(void)
{
- uint64_t interval, start;
+ uint64_t ap_val, bp_val, end, lag;
- interval = (uint64_t)usecs * tsc_frequency / 1000000;
- start = rdtsc_lfence();
- while (rdtsc_lfence() - start < interval)
- CPU_BUSY_CYCLE();
+ bp_val = rdtsc_lfence();
+ end = bp_val + tsc_test_cycles;
+ while (__predict_false(bp_val < end)) {
+ ap_val = tsc_ap_status.val;
+ bp_val = rdtsc_lfence();
+ tsc_bp_status.val = bp_val;
+
+ if (__predict_false(bp_val < ap_val)) {
+ tsc_bp_status.lag_count++;
+ lag = ap_val - bp_val;
+ if (tsc_bp_status.lag_max < lag)
+ tsc_bp_status.lag_max = lag;
+ }
+ }
}
+
+#endif /* MULTIPROCESSOR */
Index: sys/arch/amd64/amd64/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/cpu.c,v
retrieving revision 1.156
diff -u -p -r1.156 cpu.c
--- sys/arch/amd64/amd64/cpu.c 26 Apr 2022 08:35:30 -0000 1.156
+++ sys/arch/amd64/amd64/cpu.c 31 Jul 2022 03:06:40 -0000
@@ -772,9 +772,9 @@ cpu_init(struct cpu_info *ci)
lcr4(cr4 & ~CR4_PGE);
lcr4(cr4);
- /* Synchronize TSC */
+ /* Check if TSC is synchronized. */
if (cold && !CPU_IS_PRIMARY(ci))
- tsc_sync_ap(ci);
+ tsc_test_sync_ap(ci);
#endif
}
@@ -854,18 +854,14 @@ cpu_start_secondary(struct cpu_info *ci)
#endif
} else {
/*
- * Synchronize time stamp counters. Invalidate cache and
- * synchronize twice (in tsc_sync_bp) to minimize possible
- * cache effects. Disable interrupts to try and rule out any
- * external interference.
+ * Test if TSCs are synchronized. Invalidate cache to
+ * minimize possible cache effects. Disable interrupts to
+ * try to rule out external interference.
*/
s = intr_disable();
wbinvd();
- tsc_sync_bp(ci);
+ tsc_test_sync_bp(ci);
intr_restore(s);
-#ifdef TSC_DEBUG
- printf("TSC skew=%lld\n", (long long)ci->ci_tsc_skew);
-#endif
}
if ((ci->ci_flags & CPUF_IDENTIFIED) == 0) {
@@ -890,7 +886,6 @@ void
cpu_boot_secondary(struct cpu_info *ci)
{
int i;
- int64_t drift;
u_long s;
atomic_setbits_int(&ci->ci_flags, CPUF_GO);
@@ -905,18 +900,11 @@ cpu_boot_secondary(struct cpu_info *ci)
db_enter();
#endif
} else if (cold) {
- /* Synchronize TSC again, check for drift. */
- drift = ci->ci_tsc_skew;
+ /* Test if TSCs are synchronized again. */
s = intr_disable();
wbinvd();
- tsc_sync_bp(ci);
+ tsc_test_sync_bp(ci);
intr_restore(s);
- drift -= ci->ci_tsc_skew;
-#ifdef TSC_DEBUG
- printf("TSC skew=%lld drift=%lld\n",
- (long long)ci->ci_tsc_skew, (long long)drift);
-#endif
- tsc_sync_drift(drift);
}
}
@@ -942,13 +930,12 @@ cpu_hatch(void *v)
#endif
/*
- * Synchronize the TSC for the first time. Note that interrupts are
- * off at this point.
+ * Test if our TSC is synchronized for the first time.
+ * Note that interrupts are off at this point.
*/
wbinvd();
ci->ci_flags |= CPUF_PRESENT;
- ci->ci_tsc_skew = 0; /* reset on resume */
- tsc_sync_ap(ci);
+ tsc_test_sync_ap(ci);
lapic_enable();
lapic_startclock();
Index: sys/arch/amd64/include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/cpu.h,v
retrieving revision 1.145
diff -u -p -r1.145 cpu.h
--- sys/arch/amd64/include/cpu.h 12 Jul 2022 04:46:00 -0000 1.145
+++ sys/arch/amd64/include/cpu.h 31 Jul 2022 03:06:40 -0000
@@ -207,8 +207,6 @@ struct cpu_info {
paddr_t ci_vmxon_region_pa;
struct vmxon_region *ci_vmxon_region;
- int64_t ci_tsc_skew; /* counter skew vs cpu0 */
-
char ci_panicbuf[512];
paddr_t ci_vmcs_pa;
@@ -228,7 +226,6 @@ struct cpu_info {
#define CPUF_INVAR_TSC 0x0100 /* CPU has invariant TSC */
#define CPUF_USERXSTATE 0x0200 /* CPU has curproc's xsave
state */
-#define CPUF_SYNCTSC 0x0800 /* Synchronize TSC */
#define CPUF_PRESENT 0x1000 /* CPU is present */
#define CPUF_RUNNING 0x2000 /* CPU is running */
#define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */
Index: sys/arch/amd64/include/cpuvar.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/cpuvar.h,v
retrieving revision 1.11
diff -u -p -r1.11 cpuvar.h
--- sys/arch/amd64/include/cpuvar.h 16 May 2021 04:33:05 -0000 1.11
+++ sys/arch/amd64/include/cpuvar.h 31 Jul 2022 03:06:40 -0000
@@ -97,8 +97,7 @@ void identifycpu(struct cpu_info *);
void cpu_init(struct cpu_info *);
void cpu_init_first(void);
-void tsc_sync_drift(int64_t);
-void tsc_sync_bp(struct cpu_info *);
-void tsc_sync_ap(struct cpu_info *);
+void tsc_test_sync_bp(struct cpu_info *);
+void tsc_test_sync_ap(struct cpu_info *);
#endif
Index: sys/sys/timetc.h
===================================================================
RCS file: /cvs/src/sys/sys/timetc.h,v
retrieving revision 1.12
diff -u -p -r1.12 timetc.h
--- sys/sys/timetc.h 6 Jul 2020 13:33:09 -0000 1.12
+++ sys/sys/timetc.h 31 Jul 2022 03:06:40 -0000
@@ -120,6 +120,7 @@ extern struct timekeep *timekeep;
u_int64_t tc_getfrequency(void);
u_int64_t tc_getprecision(void);
void tc_init(struct timecounter *tc);
+void tc_reset_quality(struct timecounter *, int);
void tc_setclock(const struct timespec *ts);
void tc_setrealtimeclock(const struct timespec *ts);
void tc_ticktock(void);
Index: sys/kern/kern_tc.c
===================================================================
RCS file: /cvs/src/sys/kern/kern_tc.c,v
retrieving revision 1.76
diff -u -p -r1.76 kern_tc.c
--- sys/kern/kern_tc.c 23 Jul 2022 22:58:51 -0000 1.76
+++ sys/kern/kern_tc.c 31 Jul 2022 03:06:40 -0000
@@ -458,6 +458,38 @@ tc_init(struct timecounter *tc)
timecounter = tc;
}
+/*
+ * Change the given timecounter's quality. If it is the active
+ * counter and it is no longer the best counter, activate the
+ * best counter.
+ */
+void
+tc_reset_quality(struct timecounter *tc, int quality)
+{
+ struct timecounter *best = &dummy_timecounter, *tmp;
+
+ if (tc == &dummy_timecounter)
+ panic("%s: cannot change dummy counter quality", __func__);
+
+ tc->tc_quality = quality;
+ if (timecounter == tc) {
+ SLIST_FOREACH(tmp, &tc_list, tc_next) {
+ if (tmp->tc_quality < 0)
+ continue;
+ if (tmp->tc_quality < best->tc_quality)
+ continue;
+ if (tmp->tc_quality == best->tc_quality &&
+ tmp->tc_frequency < best->tc_frequency)
+ continue;
+ best = tmp;
+ }
+ if (best != tc) {
+ enqueue_randomness(best->tc_get_timecount(best));
+ timecounter = best;
+ }
+ }
+}
+
/* Report the frequency of the current timecounter. */
u_int64_t
tc_getfrequency(void)
