glxclk(4) has been compiled-but-disabled for over six months. It was
disabled when loongson made the clockintr switch. Nobody has asked me
to make it an intrclock option for loongson so I assume the mips64 CP0
interrupt clock is sufficient.
This patch deletes the driver, driver config glue, manpage, and
manpage cross-references. Not sure if I got it all. I have no
system to test this with.
One thing I noticed: glxclk(4) is compiled into loongson GENERIC but
not loongson RAMDISK. A bit odd for a clock interrupt driver, no? I
figure you would want to be sure certain such a basic component was
working during installation, but maybe I'm missing something.
Anyway, did I get everything? If so, ok?
Index: sys/arch/loongson/dev/glxclk.c
===================================================================
RCS file: sys/arch/loongson/dev/glxclk.c
diff -N sys/arch/loongson/dev/glxclk.c
--- sys/arch/loongson/dev/glxclk.c 19 Nov 2022 16:23:48 -0000 1.8
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,338 +0,0 @@
-/* $OpenBSD: glxclk.c,v 1.8 2022/11/19 16:23:48 cheloha Exp $ */
-
-/*
- * Copyright (c) 2013 Paul Irofti.
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/device.h>
-#include <sys/kernel.h>
-
-#include <machine/bus.h>
-#include <machine/autoconf.h>
-
-#include <dev/isa/isavar.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcidevs.h>
-
-#include <dev/pci/glxreg.h>
-#include <dev/pci/glxvar.h>
-
-struct glxclk_softc {
- struct device sc_dev;
-
- bus_space_tag_t sc_iot;
- bus_space_handle_t sc_ioh;
-};
-
-struct cfdriver glxclk_cd = {
- NULL, "glxclk", DV_DULL
-};
-
-int glxclk_match(struct device *, void *, void *);
-void glxclk_attach(struct device *, struct device *, void *);
-int glxclk_intr(void *);
-int glxclk_stat_intr(void *arg);
-void glxclk_startclock(struct cpu_info *);
-
-const struct cfattach glxclk_ca = {
- sizeof(struct glxclk_softc), glxclk_match, glxclk_attach,
-};
-
-#define MSR_LBAR_ENABLE 0x100000000ULL
-#define MSR_LBAR_MFGPT DIVIL_LBAR_MFGPT
-#define MSR_MFGPT_SIZE 0x40
-#define MSR_MFGPT_ADDR_MASK 0xffc0
-
-#define AMD5536_MFGPT1_CMP2 0x0000000a /* Compare value for
CMP2 */
-#define AMD5536_MFGPT1_CNT 0x0000000c /* Up counter */
-#define AMD5536_MFGPT1_SETUP 0x0000000e /* Setup register */
-#define AMD5536_MFGPT1_SCALE 0x7 /* Set to 128 */
-#define AMD5536_MFGPT1_C2_IRQM 0x00000200
-
-#define AMD5536_MFGPT2_CMP2 0x00000012 /* Compare value for
CMP2 */
-#define AMD5536_MFGPT2_CNT 0x00000014 /* Up counter */
-#define AMD5536_MFGPT2_SETUP 0x00000016 /* Setup register */
-#define AMD5536_MFGPT2_SCALE 0x3 /* Divide by 8 */
-#define AMD5536_MFGPT2_C2_IRQM 0x00000400
-
-#define AMD5536_MFGPT_CNT_EN (1 << 15) /* Enable counting */
-#define AMD5536_MFGPT_CMP2 (1 << 14) /* Compare 2 output */
-#define AMD5536_MFGPT_CMP1 (1 << 13) /* Compare 1 output */
-#define AMD5536_MFGPT_SETUP (1 << 12) /* Set to 1 after 1st write */
-#define AMD5536_MFGPT_STOP_EN (1 << 11) /* Stop enable */
-#define AMD5536_MFGPT_CMP2MODE (1 << 9)|(1 << 8)/* Set to GE +
activate IRQ */
-#define AMD5536_MFGPT_CLKSEL (1 << 4) /* Clock select 14MHz */
-
-
-struct glxclk_softc *glxclk_sc;
-
-/*
- * Statistics clock interval and variance, in usec. Variance must be a
- * power of two. Since this gives us an even number, not an odd number,
- * we discard one case and compensate. That is, a variance of 1024 would
- * give us offsets in [0..1023]. Instead, we take offsets in [1..1023].
- * This is symmetric about the point 512, or statvar/2, and thus averages
- * to that value (assuming uniform random numbers).
- */
-/* XXX fix comment to match value */
-int statvar = 8192;
-int statmin; /* statclock interval - 1/2*variance */
-
-int
-glxclk_match(struct device *parent, void *match, void *aux)
-{
- struct glxpcib_attach_args *gaa = aux;
- struct cfdata *cf = match;
-
- if (strcmp(gaa->gaa_name, cf->cf_driver->cd_name) != 0)
- return 0;
-
- return 1;
-}
-
-void
-glxclk_attach(struct device *parent, struct device *self, void *aux)
-{
- glxclk_sc = (struct glxclk_softc *)self;
- struct glxpcib_attach_args *gaa = aux;
- u_int64_t wa;
- int statint, minint;
-
- printf(" not configured\n");
- return;
-
- glxclk_sc->sc_iot = gaa->gaa_iot;
- glxclk_sc->sc_ioh = gaa->gaa_ioh;
-
- wa = rdmsr(MSR_LBAR_MFGPT);
-
- if ((wa & MSR_LBAR_ENABLE) == 0) {
- printf(" not configured\n");
- return;
- }
-
- if (bus_space_map(glxclk_sc->sc_iot, wa & MSR_MFGPT_ADDR_MASK,
- MSR_MFGPT_SIZE, 0, &glxclk_sc->sc_ioh)) {
- printf(" not configured\n");
- return;
- }
-
- /*
- * MFGPT runs on powers of two, adjust the hz value accordingly.
- */
- stathz = hz = 128;
- tick = 1000000 / hz;
- tick_nsec = 1000000000 / hz;
-
- printf(": clock");
-
- /* Set comparator 2 */
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_CMP2, 1);
-
- /* Reset counter to 0 */
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_CNT, 0);
-
- /*
- * All the bits in the range 11:0 have to be written at once.
- * After they're set the first time all further writes are
- * ignored.
- */
- uint16_t setup = (AMD5536_MFGPT1_SCALE | AMD5536_MFGPT_CMP2MODE |
- AMD5536_MFGPT_CMP1 | AMD5536_MFGPT_CMP2 | AMD5536_MFGPT_CNT_EN);
-
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_SETUP, setup);
-
- /* Check to see if the MFGPT_SETUP bit was set */
- setup = bus_space_read_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_SETUP);
- if ((setup & AMD5536_MFGPT_SETUP) == 0) {
- printf(" not configured\n");
- return;
- }
-
- /* Enable MFGPT1 Comparator 2 Output to the Interrupt Mapper */
- wa = rdmsr(MFGPT_IRQ);
- wa |= AMD5536_MFGPT1_C2_IRQM;
- wrmsr(MFGPT_IRQ, wa);
-
- /*
- * Tie PIC input 5 to IG7 for glxclk(4).
- */
- wa = rdmsr(PIC_ZSEL_LOW);
- wa &= ~(0xfUL << 20);
- wa |= 7 << 20;
- wrmsr(PIC_ZSEL_LOW, wa);
-
- /* Start the counter */
- setup = (AMD5536_MFGPT_CNT_EN | AMD5536_MFGPT_CMP2);
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_SETUP, setup);
-
- /*
- * The interrupt argument is NULL in order to notify the dispatcher
- * to pass the clock frame as argument. This trick also forces keeping
- * the soft state global because during the interrupt we need to clear
- * the comp2 event in the MFGPT setup register.
- */
- isa_intr_establish(sys_platform->isa_chipset, 7, IST_PULSE, IPL_CLOCK,
- glxclk_intr, NULL, "clock");
-
- md_startclock = glxclk_startclock;
-
- printf(", prof");
-
-
- /*
- * Try to be as close as possible, w/o the variance, to the hardclock.
- * The stat clock has its source set to the 14MHz clock so that the
- * variance interval can be more generous.
- *
- * Experience shows that the clock source goes crazy on scale factors
- * lower than 8, so keep it at 8 and adjust the counter (statint) so
- * that it results a 128Hz statclock, just like the hardclock.
- */
- statint = 16000;
- minint = statint / 2 + 100;
- while (statvar > minint)
- statvar >>= 1;
-
- /* Set comparator 2 */
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_CMP2, statint);
- statmin = statint - (statvar >> 1);
-
- /* Reset counter to 0 */
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_CNT, 0);
-
- /*
- * All the bits in the range 11:0 have to be written at once.
- * After they're set the first time all further writes are
- * ignored.
- */
- setup = (AMD5536_MFGPT2_SCALE | AMD5536_MFGPT_CMP2MODE |
- AMD5536_MFGPT_CLKSEL | AMD5536_MFGPT_CMP1 | AMD5536_MFGPT_CMP2 |
- AMD5536_MFGPT_CNT_EN);
-
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_SETUP, setup);
-
- /* Check to see if the MFGPT_SETUP bit was set */
- setup = bus_space_read_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_SETUP);
- if ((setup & AMD5536_MFGPT_SETUP) == 0) {
- printf(" not configured\n");
- return;
- }
-
- /* Enable MFGPT2 Comparator 2 Output to the Interrupt Mapper */
- wa = rdmsr(MFGPT_IRQ);
- wa |= AMD5536_MFGPT2_C2_IRQM;
- wrmsr(MFGPT_IRQ, wa);
-
- /*
- * Tie PIC input 6 to IG8 for glxstat(4).
- */
- wa = rdmsr(PIC_ZSEL_LOW);
- wa &= ~(0xfUL << 24);
- wa |= 8 << 24;
- wrmsr(PIC_ZSEL_LOW, wa);
-
- /*
- * The interrupt argument is NULL in order to notify the dispatcher
- * to pass the clock frame as argument. This trick also forces keeping
- * the soft state global because during the interrupt we need to clear
- * the comp2 event in the MFGPT setup register.
- */
- isa_intr_establish(sys_platform->isa_chipset, 8, IST_PULSE,
- IPL_STATCLOCK, glxclk_stat_intr, NULL, "prof");
-
- printf("\n");
-}
-
-void
-glxclk_startclock(struct cpu_info *ci)
-{
- /* Start the clock. */
- int s = splclock();
- ci->ci_clock_started++;
- splx(s);
-}
-
-int
-glxclk_intr(void *arg)
-{
- struct clockframe *frame = arg;
- uint16_t setup = 0;
- struct cpu_info *ci = curcpu();
-
- /* Clear the current event */
- setup = bus_space_read_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_SETUP);
- setup |= AMD5536_MFGPT_CMP2;
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT1_SETUP, setup);
-
- if (ci->ci_clock_started == 0)
- return 1;
-
- hardclock(frame);
-
- return 1;
-}
-
-int
-glxclk_stat_intr(void *arg)
-{
- struct clockframe *frame = arg;
- uint16_t setup = 0;
- struct cpu_info *ci = curcpu();
- u_long newint, r, var;
-
- /* Clear the current event */
- setup = bus_space_read_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_SETUP);
- setup |= AMD5536_MFGPT_CMP2;
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_SETUP, setup);
-
- if (ci->ci_clock_started == 0)
- return 1;
-
- statclock(frame);
-
- /*
- * Compute new randomized interval. The intervals are uniformly
- * distributed on [statint - statvar / 2, statint + statvar / 2],
- * and therefore have mean statint, giving a stathz frequency clock.
- */
- var = statvar;
- do {
- r = random() & (var - 1);
- } while (r == 0);
- newint = statmin + r;
-
- bus_space_write_2(glxclk_sc->sc_iot, glxclk_sc->sc_ioh,
- AMD5536_MFGPT2_CMP2, newint);
-
- return 1;
-}
Index: sys/arch/loongson/conf/files.loongson
===================================================================
RCS file: /cvs/src/sys/arch/loongson/conf/files.loongson,v
retrieving revision 1.26
diff -u -p -r1.26 files.loongson
--- sys/arch/loongson/conf/files.loongson 30 Sep 2020 22:23:41 -0000
1.26
+++ sys/arch/loongson/conf/files.loongson 6 Jul 2023 02:26:07 -0000
@@ -126,10 +126,6 @@ device apm
attach apm at mainbus
file arch/loongson/dev/apm.c apm needs-flag
-device glxclk
-attach glxclk at glxpcib
-file arch/loongson/dev/glxclk.c glxclk
-
define leiobus {}
device leioc: leiobus
Index: sys/arch/loongson/conf/GENERIC
===================================================================
RCS file: /cvs/src/sys/arch/loongson/conf/GENERIC,v
retrieving revision 1.66
diff -u -p -r1.66 GENERIC
--- sys/arch/loongson/conf/GENERIC 10 Aug 2022 11:05:50 -0000 1.66
+++ sys/arch/loongson/conf/GENERIC 6 Jul 2023 02:26:07 -0000
@@ -47,7 +47,6 @@ pci* at ppb?
glxpcib* at pci?
gpio* at glxpcib?
isa0 at glxpcib?
-glxclk* at glxpcib?
iic* at glxpcib?
mcclock0 at isa? port 0x70
pckbc0 at isa? # Yeeloong only
Index: share/man/man4/man4.loongson/glxclk.4
===================================================================
RCS file: share/man/man4/man4.loongson/glxclk.4
diff -N share/man/man4/man4.loongson/glxclk.4
--- share/man/man4/man4.loongson/glxclk.4 17 Feb 2022 12:24:08 -0000
1.8
+++ /dev/null 1 Jan 1970 00:00:00 -0000
@@ -1,55 +0,0 @@
-.\" $OpenBSD: glxclk.4,v 1.8 2022/02/17 12:24:08 jsg Exp $
-.\"
-.\" Copyright (c) 2013 Paul Irofti.
-.\"
-.\" Permission to use, copy, modify, and distribute this software for any
-.\" purpose with or without fee is hereby granted, provided that the above
-.\" copyright notice and this permission notice appear in all copies.
-.\"
-.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-.\"
-.Dd $Mdocdate: February 17 2022 $
-.Dt GLXCLK 4 loongson
-.Os
-.Sh NAME
-.Nm glxclk
-.Nd AMD Geode CS5536 multi-function general purpose timer
-.Sh SYNOPSIS
-.Cd "glxclk* at glxpcib?"
-.Sh DESCRIPTION
-The
-.Nm
-driver enables two of the multi-function general purpose timers found on the
-Geode companion chip to be used as the system clock and the statistics clock.
-.Pp
-The statistics clock is implemented with interval variance support based on
-Chris Torek's paper on randomized sampling.
-.Sh SEE ALSO
-.Xr glxpcib 4 ,
-.Xr intro 4
-.Rs
-.%A Steven McCanne
-.%A Chris Torek
-.%T "A Randomized Sampling Clock for CPU Utilization Estimation and Code
Profiling"
-.%B "In Proc. Winter 1993 USENIX Conference"
-.%D 1993
-.%P pp. 387\(en394
-.%I USENIX Association
-.Re
-.Sh HISTORY
-The
-.Nm
-driver first appeared in
-.Ox 5.3 .
-.Sh AUTHORS
-.An -nosplit
-The
-.Nm
-driver was written by
-.An Paul Irofti Aq Mt [email protected] .
Index: share/man/man4/man4.loongson/Makefile
===================================================================
RCS file: /cvs/src/share/man/man4/man4.loongson/Makefile,v
retrieving revision 1.11
diff -u -p -r1.11 Makefile
--- share/man/man4/man4.loongson/Makefile 30 Sep 2020 22:23:40 -0000
1.11
+++ share/man/man4/man4.loongson/Makefile 6 Jul 2023 02:26:07 -0000
@@ -1,6 +1,6 @@
# $OpenBSD: Makefile,v 1.11 2020/09/30 22:23:40 patrick Exp $
-MAN= apm.4 autoconf.4 bonito.4 gdiumiic.4 glxclk.4 glxpcib.4 htb.4 intro.4 \
+MAN= apm.4 autoconf.4 bonito.4 gdiumiic.4 glxpcib.4 htb.4 intro.4 \
leioc.4 mem.4 sisfb.4 smfb.4 stsec.4 voyager.4 ykbec.4
MANSUBDIR=loongson
Index: share/man/man4/man4.loongson/glxpcib.4
===================================================================
RCS file: /cvs/src/share/man/man4/man4.loongson/glxpcib.4,v
retrieving revision 1.7
diff -u -p -r1.7 glxpcib.4
--- share/man/man4/man4.loongson/glxpcib.4 24 Nov 2013 12:58:17 -0000
1.7
+++ share/man/man4/man4.loongson/glxpcib.4 6 Jul 2023 02:26:07 -0000
@@ -13,7 +13,6 @@
.Cd "glxpcib* at pci?"
.\" .Cd "gpio* at glxpcib?"
.\" .Cd "iic* at glxpcib?"
-.Cd "glxclk* at glxpcib?"
.Cd "isa* at glxpcib?"
.Sh DESCRIPTION
The
@@ -28,7 +27,6 @@ driver implements a 32-bit 3.5 MHz timec
.Sh SEE ALSO
.\" .Xr gpio 4 ,
.\" .Xr iic 4 ,
-.Xr glxclk 4 ,
.Xr intro 4 ,
.Xr isa 4 ,
.Xr pci 4 ,
Index: distrib/sets/lists/man/mi
===================================================================
RCS file: /cvs/src/distrib/sets/lists/man/mi,v
retrieving revision 1.1703
diff -u -p -r1.1703 mi
--- distrib/sets/lists/man/mi 2 Jul 2023 12:45:01 -0000 1.1703
+++ distrib/sets/lists/man/mi 6 Jul 2023 02:26:08 -0000
@@ -1622,7 +1622,6 @@
./usr/share/man/man4/loongson/autoconf.4
./usr/share/man/man4/loongson/bonito.4
./usr/share/man/man4/loongson/gdiumiic.4
-./usr/share/man/man4/loongson/glxclk.4
./usr/share/man/man4/loongson/glxpcib.4
./usr/share/man/man4/loongson/htb.4
./usr/share/man/man4/loongson/intro.4
