On Thu, Aug 03, 2023 at 08:11:40PM +0200, Robert Palm wrote:
> I am looking at following code from arm64 and riscv64.
>
> ARM64:
> https://github.com/openbsd/src/blob/master/sys/arch/arm64/include/signal.h#L51
>
> --------------------------------------------------
> struct sigcontext {
> int __sc_unused;
> int sc_mask; /* signal mask to restore */
>
> unsigned long sc_sp;
> unsigned long sc_lr;
> unsigned long sc_elr;
> unsigned long sc_spsr;
> unsigned long sc_x[30];
>
> long sc_cookie;
> };
> --------------------------------------------------
>
> RISCV64:
> https://github.com/openbsd/src/blob/master/sys/arch/riscv64/include/signal.h#L48
>
> --------------------------------------------------
> struct sigcontext {
> int __sc_unused;
> int sc_mask;
>
> __register_t sc_ra;
> __register_t sc_sp;
> __register_t sc_gp;
> __register_t sc_tp;
> __register_t sc_t[7];
> __register_t sc_s[12];
> __register_t sc_a[8];
> __register_t sc_sepc;
>
> /* 64 bit floats as well as integer registers */
> __register_t sc_f[32]; /* floating-point registers */
> __register_t sc_fcsr; /* floating-point control register */
>
> long sc_cookie;
> };
>
> --------------------------------------------------
>
> I would like to know what these registers "mean".
>
> Maybe someone knows and can tell me ?
>
> Thank you.
>
Hi!
On my riscv64 qemu instance I looked in /usr/include/machine/_types.h
(probably the same as /sys/arch/riscv64/include/_types.h)
and this is what it said:
/* Register size */
typedef long __register_t;
A long in OpenBSD/riscv64 is 8 bytes so 64 bits.
riscv64# cat > sizetest.c
#include <stdio.h>
int
main(void)
{
return (sizeof(long));
}
riscv64# cc -g -o sizetest sizetest.c
riscv64# ./sizetest
riscv64# echo $?
8
I noticed in /sys/arch/riscv64/include/reg.h there is a register which is not
listed in the riscv64 register list in my literature really there is registers
x0 through x31 so 32 long registers, there also is 32 floating point registers
if your implementation has that mostly it does when the riscv cpu reports
IMAFDQ or similar which is (integer ISA, multiply/divide set, atomic set,
floating points set, double floats set, and quad precision floating points).
Is this what you want to hear? The number of registers is not wrong but
it doesn't have x0 which is a constant value of 0. Perhaps the
/sys/arch/riscv64/riscv64/db_interface.c has more about the registers to your
liking, near struct db_variable db_regs[]...
I got some help from my (by now pre-pandemic era books) written by David
Patterson which cover riscv in some detail. Otherwise I just looked at
the https://en.wikipedia.org/wiki/RISC-V near Register sets which seems
to be an excellent reference.
Best Regards,
-peter
--
Over thirty years experience on Unix-like Operating Systems starting with QNX.
