Hi Harlan, >In the "Figure 1" case "core" packet timestamps come from the kernel and the >new packet timestamp will be added by the hardware engine. >I understand the following question is outside the scope of this document, but >how can one determine how well sync'd the internal clock is with the clock in >the accurate timestamp engine?
Well, indeed it is strictly an implementation question. For example, in typical PTP implementations (that I am familiar with) the accurate clock is only maintained in one place, i.e., in the HW engine. The SW stack includes the servo algorithm; the SW stack regularly computes the necessary offset or frequency adjustments, and whenever necessary sends update commands to the HW engine about these adjustments. Thus, the SW stack does not need to maintain an additional clock, since all its computations are performed WRT the HW clock. Thanks, Tal. -----Original Message----- From: Harlan Stenn [mailto:[email protected]] Sent: Monday, October 28, 2013 10:09 AM To: Tal Mizrahi Cc: [email protected]; [email protected]; [email protected] Subject: Re: [ntpwg] New version of draft-mizrahi-ntp-checksum-trailer Just some thoughts, and I hope I'm awake enough to type this... There seem to be several issues here. In the "Figure 1" case "core" packet timestamps come from the kernel and the new packet timestamp will be added by the hardware engine. I understand the following question is outside the scope of this document, but how can one determine how well sync'd the internal clock is with the clock in the accurate timestamp engine? If we have TX and RX hardware timestamping capabilities, we can use NTP's interleave mode to communicate these timestamps as well. Having said that, I'm sure there is something to be learned from implementing Tal's proposal. H _______________________________________________ TICTOC mailing list [email protected] https://www.ietf.org/mailman/listinfo/tictoc
