Hi All,

Earlier, I explained that my application require very good relative
stability between various GPSDOs.

A rough estimate of my requirements is:

-Baselines of 100s of meters to 10s of kilometres. 

-Sub-nanosecond relative stability (this I forgot to mention earlier -
thanks to TvB for reminding me).
-Time scales of maybe 100s of seconds to 10s of minutes. 

-The lower limit on my stability requirement is maybe the 200ps of jitter
that the FPGA will add to the processed data.

My question is this:

At this stage I'm not sure what all the various causes are for the error in
the 1PPS output of a GPS receiver. (I sure I will find the answer to this in
all that references TvB and Magnus gave me).

However, a quick guess would be the delay caused by atmospheric effects (I
don't think thermal noise would play a big role since the antenna is looking
straight up) Also, there will be errors higher up in the food chain, such as
changes in satellite orbits etc. I guess these errors are fairly systematic.
Lower down in the food chain, I presume the M12+T adds further errors to the
signal (viz. the antenna, LNA, TCXO jitter, etc). I presume these errors
would be on faster time scales, smaller and much more stochastic in nature. 

If the resolution of my phase comparator is about 100ps, and keeping in mind
that I want relative stability, wouldn't it make sense to lock the M12+T's
on-board TCXO to the OCXO (probably not straight forward to do)? I realise
that one would lose the advantage of any dithering effect which would
quickly average any zero mean effect. I guess this will depend on the nature
of the errors introduced due to clock jitter: Is it Gaussian and zero mean?
I guess one will have to investigate what happens at down-conversion to IF
etc. And, that ultimately it will depend on the size and nature of noise
caused by the TCXO.

If one could closely follow the drifts in atmospheric effects (which would
be the same for short baselines) one will have very good relative stability.

Regards,

Stephan 



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