Jack Hudler wrote: > Bruce, > > Can you describe further your idea about phase detection using an ADC. > > Who produces the sinewave from the filtered counter? > > (Thinking out loud) Using a 10MHz oscillator as an example: > Is this dividing the clock down to (say) 1 MHz and using a square->sine > conversion then sampling the phase angle at the 1PPS transition? The accuracy > of > square->sine conversion appears as another source of error. > > Perhaps the MAX9382 (http://www.maxim-ic.com/appnotes.cfm/appnote_number/1130) > could help with the problem of locking to the undesired harmonic. > > Jack > > -----Original Message----- > From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf > Of Dr Bruce Griffiths > Sent: Wednesday, December 13, 2006 7:52 PM > To: Discussion of precise time and frequency measurement > Subject: Re: [time-nuts] LPRO-101 with Brooks Shera's GPS locking circuit > > > The Brooks Shera circuit relies on the 24 MHz oscillator not being > locked to the OCXO or the PPS signal so that (in the absence of > injection locking) averaging the measured time interval gives an > unbiased estimate of the true value. Using a higher speed oscillator to > measure the time interval would be advantageous with the more accurate > GPS timing receivers currently available. If you have an M12+ or MTM > timing receiver and a rubidium oscillator the Brooks Shera technique is > not optimum you can easily achieve a performance that is 1-2 orders of > magnitude better with a less complex phase detector. The Brooks Shera > circuit has a single shot resolution of 41.6 nanosec which may be up to > 10 times worse than the jitter in the PPS output of a good timing > receiver (after correcting for any sawtooth error - in software of > course, to avoid any additional noise and errors caused by hardware > correction). > > The phase detector method employed is the digital equivalent of a > classical sampling phase detector with a linear phase detection > characteristic. A phase lock loop employing a sampling phase detector > will lock to a harmonic of the sampling frequency, which in this case is > 1Hz. It is therefore necessary to divide down the OCXO (or other high > stability oscillator) frequency to a value such that the efc tuning > range of the oscillator precludes locking to the undesired harmonic. > Unfortunately a phase detector with a linear characteristic can > sometimes allow the phase lock loop to lock to a frequency which is not > a harmonic of the sampling frequency (in this case frequencies like > 17/13, 12/11 Hz etc.). > > A phase detector with a sinusoidal characteristic (such as an ADC > sampling a sinewave produced by filtering the output of a counter > clocked by the OCXO) avoids the problem of non harmonic locking and > eliminates most of the digital circuitry. > > A loop time constant of around 120 seconds is far too short for > obtaining the optimum performance from a good rubidium standard, as the > loop will degrade the rubidium standard to an accuracy of around 35E-10 > (with a 41.6ns single shot measurement resolution) when a good rubidium > standard is capable of a considerably higher stability than this. > > Bruce > > _______________________________________________ > time-nuts mailing list > time-nuts@febo.com > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > > > > _______________________________________________ > time-nuts mailing list > time-nuts@febo.com > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > > Jack
To produce the sinewave just divide down the output of the oscillator to be disciplined to a suitable frequency with a low jitter digital counter/divider. You will need to use a very quiet well filtered power supply to reduce the divider output jitter particularly if a CMOS divider is used. A 50% duty cycle divider output is optimum, as ideally its spectral content only includes the fundamental plus odd harmonics (lowest harmonic is the 3rd). Then filter the divider output with an analog (LC) low pass filter. As long as the inductors and capacitors in the filter are linear then the resultant output sinewave will have low distortion if the filter has sufficient sections to attenuate the unwanted harmonics. The filter will, of course, phase shift the filtered output so that its zero crossings are displaced from the divider output zero crossings and this phase shift will vary with time and temperature. Low temperature coefficient inductors and capacitors are desirable to minimise the temperature coefficient of this phase shift. However if necessary, it is possible to measure this phase shift automatically between the PPS pulses. The phase lock loop will lock the sinewave signal zero crossing with the correct slope to the leading edge of the PPS signal. Thus the oscillator frequency will be locked to the PPS signals albeit with a phase shift due to the divider propagation delay and the filter phase shift. Linear Technology, Analog Devices and others make suitable SAR (successive approximation) ADCs that can sample 1MHz sinewaves with low distortion with a 1Hz sampling clock (PPS signal). The output of the ADC is used in effect just like the output of an equivalent analog sampling phase detector sampling a sinewave oscillator output. Some digital filtering of the sequence of ADC samples can be done before using the samples as the error input to a 2nd or 3rd order phase lock loop. For best accuracy the GPS timing receiver's PPS sawtooth correction should be applied to each ADC sample before filtering. The maxim MAX9382 is a digital phase detector, such phase detectors are far from optimum for locking the oscillator output to the noisy PPS signal. To use this device one would have to divide the frequency of the oscillator down to 1Hz, and use very long time constants in the analog loop filters. Ensuring locking to the correct harmonic is simple, just ensure that locking to the correct one is the only possibility. For example, with a 1MHz sinewave reference for the phase detector, if the oscillator only has an efc tuning range of say 1E-7 then since the possible harmonics to which the phase lock loop may lock are spaced by 1E-6 of the oscillator frequency, since this exceeds the electronic tuning range, then it is easy to adjust the coarse tuning of the oscillator so that only locking to the correct harmonic can occur. The sinewave reference can be used in what is essentially a form of delay locked loop to lock the zero crossings of reference to the oscillator output. Alternatively equivalent time sampling techniques can be used to determine the reference sine wave amplitude and phase shift with respect to the oscillator output. Bruce _______________________________________________ time-nuts mailing list time-nuts@febo.com https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
