Hi Said,
The DDS idea that you (and Ulrich) suggest sounds like a good plan.
However, to me your predictions sound overly optimistic.
>Said wrote:
>But let's say these are as good as advertised, and for me that would mean
>say better than -95dBc/Hz at 10Hz offset from 1GHz carrier, then by reduction
>through the DDS, we would theoretically get -20dB below this, or -115dBc/Hz at
>100MHz output.
Phase noise of -115dBc/Hz @ 10Hz for a 100MHz carrier sounds a bit
steep when compared to one of Wenzel's ultra low noise ULN series
which achieves -125dBc/Hz @ 100Hz. (these oscillators are probably the
best you can buy). I guess it will probably climb to about -112dBc/Hz
@ 10Hz. Your prediction postulate that the close-in phase noise of two
devices, the digitally down divided 100MHz and the state-of-the-art
100MHz low-noise oscillator, will be comparable. I don't mean to
contradict you, since I am really not an expert, but this spec sounds
a little suspect. Maybe there is something I am missing? If this spec
is correct, I am strongly considering it.
I agree with Ulrich that the best solution is probably dependent on
the application. So let me explain my situation:
I need a 100MHz reference to clock a radar system. In other words,
I'll be clocking a DDS and some ADCs. Thus, I need low high frequency
jitter (i.e. low noise floor). I also phase-lock (this is a digital
PLL) the 100MHz to a 2.4GHz PLL for the carrier. The radar does
Doppler measurements on the carrier – so I need low close-in phase
noise. I would also like to operate the radar bi-statically (Tx and Rx
not co-located). This requires the carrier phases of the two radar
stations to be synced. Thus, I am concerned with good Allan deviation.
Quite a tall order – I admit!
I'm using Analog's AD9512 to distribute the clocks to the different
devices. It provides low skew outputs and the LVPECL has got the
following additive phase noise specs: (I hope this table display
correctly)
LVPECL Outputs 10MHz OCXO 10x Multiplied Diverence
Hz dBc/Hz dBc/Hz dBc/Hz
dBc/Hz
1 ? -100
-80 17
10 -127 -130 -110
13
100 -145 -152 -132
13
1k -153 -160 -140
13
10k -158 -165 -145
13
100k -158 -165 -145
13
1M -158 -165 -145
13
You can see from the figure that by multiplying the GPS disciplined
10MHz by 10 I will be about 13dBs short of the AD9512's potential. For
the moment, the noise limit of the AD9512 should be adequate because
at these levels because noise in other parts of the radar will then
start to dominate. However, I will certainly want to max out the
AD9512's potential.
I could lock the 10MHz to a 100MHz OCXO. However, this will probably
have to be done digitally – out of cost view point. Do you think a
digital PLL will do? Or will the digital dividers add to much noise?
Maybe the DDS idea? Or should I stick to the multiplier idea? Analog
multipliers are awfully expensive to digital alternatives.
I couldn't really find specs to compare the performances of the
different ideas yet.
Regards,
Stephan.
On 3/1/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
>
> In a message dated 3/1/2007 05:50:30 Pacific Standard Time,
> [EMAIL PROTECTED] writes:
>
> Hi Said,
>
> It seems there are indeed many ways to kill a cat. What happens to the
> close-in phase noise using this method?
>
> Cheers,
>
> Stephan.
>
>
>
> Hi Stephan,
>
> you are asking the right questions :)
>
> The near-carrier phase noise depends on the 1GHz reference source:
>
> 1) If it is a crystal such as the Xpresso 1GHz series from Fox, then the
> phase noise of the 1GHz reference will actually be reduced by 20dB for every
> 1:10 reduction in output frequency!
>
> 2) If you are using a standard (noisy) VCO, then the phase noise of your
> 10MHz reference source will be increased (multiplied) by the standard 20dB
> for every 10x increase in output frequency.
>
> This is due to the fact that when using a VCO, the PLL will use the
> reference crystal to actually reduce the phase noise of the VCO. You will
> likely use
> a loop filter with 1 - 15KHz BW. So you get the 10MHz reference noise
> multiplication inside this loop filter BW. Outside the BW, it's the DACs and
> VCO's
> noise floor.
>
> But for a crystal 1GHz reference, you would use a simple PLL with an
> extremely small loop filter BW (say <1Hz) so that your total phase noise is
> only
> dependent on the 1GHz crystal reference, and not at all on your 10MHz
> reference
> anymore. The PLL could be as simple as an Exor gate in this case.
>
> I have been trying to get phase noise/jitter specs from Fox for their new
> 1GHz Xpresso crystals, but it is hard to come by. I am waiting for feedback
> from them. They only specify "UI"!?
>
> But let's say these are as good as advertised, and for me that would mean
> say better than -95dBc/Hz at 10Hz offset from 1GHz carrier, then by reduction
> through the DDS, we would theoretically get -20dB below this, or -115dBc/Hz at
> 100MHz output.
>
> I would assume that at that point the noise floor of the DDS DAC chip is the
> limiting factor at <-150dBc/Hz as it is for the well-known AD9858 chip (it
> actually measures about -155dBc/Hz).
>
> AD has new chips coming this month, see for example the AD9957 with a 14 bit
> DAC (9858 has 10 bits), I assume these will have an even lower phase noise
> floor and very important lower spurs than the AD9858, the datasheet says TBD:
>
> _http://www.analog.com/UploadedFiles/Data_Sheets/AD9957.pdf_
> (http://www.analog.com/UploadedFiles/Data_Sheets/AD9957.pdf)
>
> Bye,
> Said
>
>
>
>
>
>
>
>
>
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