The two ways I hoped to get around the counter ripple was to measure every other set of PPS with the counter stopped in between. Or two counters running in opposite seconds, one running while the other is stopped.
Due to my error not everyone received all the discussion, my email reply puts the list address or the person who wrote the reply on a random basis. Stanley ----- Original Message ---- From: Hal Murray <[EMAIL PROTECTED]> To: Discussion of precise time and frequency measurement <time-nuts@febo.com> Sent: Wednesday, April 16, 2008 1:15:53 PM Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider? > The ECL part you've selected seems to simplify interfacing with its > synchronous enables. I think you are missing the decimal point. A synchronous enable will have setup/hold times. They will (generally) be less than the cycle time (1 ns). You aren't going to get that level of timing accuracy out of a PIC. You will have to include a (small?) cloud of high speed logic around the basic counter chip to make it work right. If you want to use ECL counters, my straw man would be a free running counter a register to grab a copy of the counter logic to load the register on the rising edge of the PPS and generate a data-ready signal for the PIC That lets you grab the counter once each second. Subtract the previous value to get the number of ticks in this second. Make the counter wide enough so you can figure out the high bits. Or feed the top bit to a counter/timer in the PIC. Or use it for the PIC's clock. If you like ECL, here is another approach: Start with a shift register runing at 1 GHz Add a holding register that grabs a copy of the shift register every N clocks. The holding register goes into an FPGA that runs at 1/N GHz You have to make 2 clocks, and you have to make sure that the holding register meets setup time at the FPGA. That determines how big you have to make N. The FPGA would look for rising edges. If not, it bumps a counter by N. If it finds one (maybe by table lookup), it adds N-x to the counter, copies the counter to a holding register, and reloads the counter to x. Pipeline as necessary. Some FPGAs have high speed serial links. The contain a PLL and a big shift register and lots of logic to do 8B/10B decoding and recognize sync patterns and ... There is usually an option to disable that logic. So you could do everything in the FPGA. Unfortunately, they tend to be the (very) expensive chips. -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ____________________________________________________________________________________ Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.