Hello Bruce, I believe a driver for an FPGA running at 350MHz was the initial query, 6GHz BW and crystal filters are probably overkill. bye, Said In a message dated 7/31/2008 01:59:34 Pacific Daylight Time, [EMAIL PROTECTED] writes:
Yes, however it is quieter and adding duty cycle stabilisation feedback fixes that problem. For even lower noise, bandpass filter the OCXO output (a crystal filter is particularly effective). Its not too difficult to drop the noise floor to a few tens of femtosec. The drawbacks being the cost, and the need to regulate the bandpass filter temperature to minimise phase shift variations with ambient temperature. You would also need to use a quieter clock driver. It may even be necessary to use a well designed bandpass limiter to increase the signal zero crossing slew rate before using a 6GHz bandwidth clock driver. However the cost and complexity probably isnt justified when driving an FPGA which may have tens of picoseconds of jitter. Bruce **************Get fantasy football with free live scoring. Sign up for FanHouse Fantasy Football today. (http://www.fanhouse.com/fantasyaffair?ncid=aolspr00050000000020) _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
