At 11:19 +1300 22-12-2008, Bruce Griffiths wrote: >Ulrich has built a circuit that takes a sampling frequency input derived >from a 10MHz GPSDO output and produces an S/PDIF output for this >application.
Most common S/PDIF receiver chips have >100ps jitter. Lower jitter implementations are available (PLL/VCXO, usually), but only in higher-end equipment. http://www.sm5bsz.com/linuxdsp/hware/delta44.htm describes a modification to a common sound card to lower its noise level; http://www.sm5bsz.com/linuxdsp/linrad.htm has software that may be useful for phase measurement. As mentioned earlier, for best noise/jitter-performance an external ADC should be used, connected through a digital link to a PC sound card. One could do a lot worse than the TI PCM4222 eval board (http://focus.ti.com/docs/prod/folders/print/pcm4222.html), which accepts an external clock if so desired. At $149 (plus a tenner or two for the sound card) this will likely be much cheaper than an equivalent FireWire-device. JDB. [more on S/PDIF sync in AES standards AES11 (sync) and AES3 (serial bitstream format)] -- LART. 250 MIPS under one Watt. Free hardware design files. http://www.lartmaker.nl/ _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
