Bruce Griffiths skrev: > Chris > > Chris Mack / N1SKY wrote: >>>> This is a good idea for testing.. >>>> >>> Applying jitter frequencies for jitter tolerance testing is standard >>> stuff and needs to be done. Jitter tolerance curves match up with MTIE >>> tolerance curves very neatly. >>> >>> >> Of course, here is the weird part... It's not SONET; but it is a chip >> that can be used for SONET... This is for a very specific form of >> audio clocking (not audiophile, nor consumer) for a mastering >> engineering application. Common input clock frequencies: 44.1kHz to >> 96kHz or also a 10MHz rubidium. >> >> The DSP PLL is this chip (I am still learning the intricacies of this >> chip): >> >> https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5326.pdf >> >> The system clock (to drive the DSP and the DSP's DCO) is essentially >> a jitter reference, pins XA and XB (differential, single ended >> capable); Jitter is transferred nearly 1:1 from XA,XB to CLK_OUT. >> This is the 38.88 MHz reference from Vectron with some skirting >> issues to be filtered before connected to the XA and XB pins. >> >> The input (on CLK_IN pins) is the source clock to be cleaned (e.g., >> 44.1kHz to 96kHz or 10MHz Rb). >> >> The output (on CLK_OUT pins) is 11 MHz to 25MHz for 256x >> oversampling master clock for ADCs and DACs >> >> 24-bit accuracy for 40kHz (88.2kHz to 96kHz sample rate encompassing >> a 45/55 anti-alias filter) shows the need for sub picosecond timing >> aperture uncertainty. >> >> > These ADCs probably have internal jitter way above a few femtosec. > >> Of course 24-bit in the real world is hard to achieve (even the new >> "32-bit" converters have a problem with it) with issues internal to >> the sampling mechanisms in a DAC / ADC, but with some out-of-band >> dither and thermal management, coupled with low jitter sampling >> clock, there may be an additional bit or so to be obtained. This is >> all part of the experiment.... >> >> >>>> I have Howard Johnson's book for >>>> >> >>>> I think a normal LC tank would be more suitable for that task. >>>> >>> It's a good introductional level book for digital signals, but isn't >>> very applicable to waveshaping or clock characterisation and testing >>> >> Yes, HJ's books leaves me wanting a little more... seems like an >> analogue / RF book for digital folks. >> >> I am looking for sharp Q to get rid of any skirt around the 38,88MHz >> of the Vectron OCXO. >> >> > Unless you are prepared to place the crystals in an oven with the > temperature regulated tightly and carefully tune the filter periodically > then using a crystal filter (or any passive filter with a sufficiently > narrow bandwidth to cleanup the skirts) will not be particularly useful. > It would be much easier to use a low bandwidth analog PLL with a low > noise VCXO to cleanup the 38.88MHz signal.
Consider using a low noise oscillator at a higher frequency and divide down. A high quality reference such as a 19,44 MHz OCXO should be the real reference, again readilly available. The typical frequency relationship is a handy 8 or 16 which allows for low noise divisions if needed. For those frequencies, SAW devices may be more suitable. >> Temperature can be obtained from cooling componentry already in situ, >> such that a known temperature is established. >> >> > > probably not much use unless one arranges to use this to tune the > crystal filter, even then thermal gradients, thermal transients and > aging will make this problematic. Sound nasty. Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.