>> ...I must admit, the tri-state PC did look good >> too until you pointed out the dead zone. I had assumed this >> would be insignificant, but of course it can't be. I'll still >> try the 74HC7046, but use the XOR PC instead. > > How about switching between the 4046's phase detectors, once the PLL has > locked?
You can do that, the PFD lock detect could be used to let a CMOS analog gate switch over. > Or using a phase comparator like the AD9901 which has a "no dead zone" XOR > phase comparator coupled with a frequency comparator? Indeed, but too narrow pulses may still be a problem. The benefit of a continous signal is that the disturbance can be kept at a high frequency and thus be dampend out and the channel capacity for corrections is maintained high. > The later one can easily be put into a small cpld if you like. You can do alot of tricks in a CPLD. Getting the basic plot of what is good or bad system design still needs to be sorted out. Not meant as criticism, but just as a kind warning. Cheers, Magnus _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
