Alan Melia wrote:
Oh yes you are not alone :-)) I have posted two or three times to EDN on this topic.
Regardless, there is a limit to just how many designs can use jittered clocks. For a number of cases one goes in the other direction. It's not that tricky to design to be within limits if one spend some thought into it. Usually, what is wise for signal integrity is wise for EMC.
Cheers, Magnus _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
