On 10/07/2010 09:34 AM, Piotr Swietochowski wrote:
Hi,
Phase startable oscillator a great invention. Do you know any papers that
implement this idea into newer technology (e.g. ASIC)? I am actually
thinking of realizing a project that would base on the Chu's invention but
will have better jitter parameters. Do you have any comments or experience
on that?
Remember that it relies on the low jitter/wander of a coax delay cable.
The actual phase startable oscillator is probably best implemented
separately, but the incident detector could be tossed into an FPGA or
CPLD. You should still be able to build one around a 2-input OR/NOR or
AND/NAND gate of choice. Remember that you do want the balanced output
since oscillator output and coax output should be separate.
A similar approach is the relaxation of an LC-tank that Bruce have been
looking at.
I doubt that this quite analogue trick would be suitable for full FPGA
implementations. The delay-chains you can set up in there vary too much
with supply and temperature, even if first degree compensation through
calibrations should come fairly cheaply.
I consider clocks and delays within an FPGA as relatively "dirty". Loads
of gates thought.
Cheers,
Magnus
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