Magnus Danielson wrote:
On 11/18/2010 02:16 AM, saidj...@aol.com wrote:
Hi Paul,
"good enough" is in the eye of the beholder..
The M12M receiver can achieve 2ns rms. So 300ns seems very bad.
Some early units had up to 1000ns error, so 300ns is quite good in that
context.
The 1 us number was never their actual performance, but the published
number from the ICD-200 spec, and it was often given for the receivers.
It was later reduced to about 340 ns with SA on... what the same old
receivers give as performance in todays spec-manship needs to be
measured. So the improvements may not have been that great actually.
1 us is "one chip" in the C/A code
System performances in direct sequence spread spectrum schemes typically
assumed that a receiver could only track the PN sequence to 1 chip. That
1 us (approximately) corresponded to a positioning uncertainty of 300m,
which was deemed "good enough for civilian use, but not good enough for
mid-course and terminal guidance of ICBM warheads", for which you'd need
something better (e.g. the 30m, 10.23MHz P/Y code). I've heard
stories about how good your accuracy needs to be to make sure you
destroy hardened silos in a "first strike" scenario.
There was a great recap of the history of GPS in GPS World a few months
ago, and I think some of this was discussed in there (certainly the
whole idea of why PN codes were selected, and the various architectures
proposed is in the recap..)
Back in the 70s and early 80s, tracking to a single chip was doing
fairly well. Most receivers of that day were procured in the context of
a systems engineering effort that flowed down a "shall have position to
500 meters" kind of requirement to a "receiver shall have timing no
worse than 1 microsecond" hardware requirement. (and the high level
requirement was almost certainly flowed back up from a "how good can we
do" expectation)
The idea of FFT based acquisition, and stuff similar to that, was a
"wouldn't it be nice",but when I was doing this stuff in the 80s, a
10MHz bandwidth real time FFT box was a pretty big unit with a whole
bunch of big boards with pipelined hardware multipliers, discrete
counters, ram chips, addressing logic, etc. (the 16x16 bit multiplier
accumulator ASIC had just come out). Maybe 50-100kg, and 50x50x80 cm,
and kilowatts of power (that straight Schottky or AS TTL draws a lot of
power)
But these days, we have signal processing that's many orders of
mangitude better (thank you Moore's law), so it's pretty easy to track
to a fraction of a chip, which observation led to deliberately adding
errors to the C/A code (selective availablity). And then, when signal
processing got even better, and people figured out how to do code-less
carrier phase tracking, etc.. even SA became obsolete.
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